Trench etch with incremental oxygen flow

Details Trench etch with incremental oxygen flow Trench etch with incremental oxygen flow

2001-09-19

2004-01-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000, C438S702000, C438S714000, C438S719000, C438S958000, C438S978000

Reexamination Certificate

active

06680232

ABSTRACT:

BACKGROUND OF THE INVENTION
Cross-sectional SEMs of trench structures show that as the pitch of the device increases greater than 1.5 &mgr;m, the sidewall profiles can change from a favorable to a non-favorable, re-entrant shape, as shown by a comparison of
FIGS. 1 and 2
.
FIG. 1
depicts a trench device structure
100
whose etched trenches
101
have a pitch of 1.5 &mgr;m. Trenches
101
are lined with gate oxide
102
and filled with doped polysilicon
103
and BPSG dielectric
104
. When the pitch is 1.5 &mgr;m or less, the filled trenches exhibit void-free fills. Such trench structures are found in integrated circuits and are used for isolation and for gates in quasi vertical DMOS (QVDOMS) devices.
As the pitch increases greater than 1.5 &mgr;m, the trench profile becomes re-entrant, i.e., the sidewalls become non-parallel as a consequence of insufficient oxygen being present during plasma etching of the trenches.
FIG. 2
depicts a trench device structure
200
whose etched trenches
201
have a pitch of 3.0 &mgr;m. Trenches
201
are lined with gate oxide
202
and filled with doped polysilicon
203
and BPSG dielectric
204
. However voids resulting from incomplete fill are formed in the subsequent polysilicon and BPSG films
203
and
204
, respectively, which adversely affects device yield. In particular, the voids lead to rupture of the gate oxide, resulting in shorting of gate-to-source current (I
gss
).
FIG. 3
shows a BPSG film
204
with voids
205
that lead to an I
gss
failure.
Lateral etching of the silicon during trench formation is commonly referred to as “bowing”. The bowing effect of lateral etching is shown in
FIG. 2
, where the upper portions
201
a
of trenches are substantially narrower than the lower trench portions
201
b.
SUMMARY OF THE INVENTION
The present invention is directed to a method for forming trenches in a device layer disposed on a silicon semiconductor substrate. The method comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts with time, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.


REFERENCES:
patent: 5077228 (1991-12-01), Eklund et al.
patent: 5607875 (1997-03-01), Nishizawa et al.
patent: 5777362 (1998-07-01), Pearce
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5828101 (1998-10-01), Endo
patent: 5920108 (1999-07-01), Hemmenway et al.
patent: 6020270 (2000-02-01), Wong et al.
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6514857 (2003-02-01), Naik et al.

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