Trench DRAM with double-gated transistor and method of...

Details Trench DRAM with double-gated transistor and method of... Trench DRAM with double-gated transistor and method of...

2005-12-20

2005-12-20

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

06977404

ABSTRACT:
A projecting semiconductor layer is formed on a major surface of a semiconductor substrate. A channel region of a first conductivity type is formed in part of the semiconductor layer. Source and drain regions of a second conductivity type are formed in the semiconductor layer such that the source and drain regions sandwich the channel region. A pair of first insulating films are formed on a surface of the channel region. A pair of gate electrodes are formed on a surface of the pair of first insulating films. A trench capacitor is provided near the source region in the semiconductor layer. A second insulating film having a greater thickness than the first insulating films is provided between surfaces of the pair of gate electrodes, which are opposed to the surfaces on which the first insulating films are formed, and a trench capacitor formed adjacent to the trench capacitor.

REFERENCES:
patent: 6121651 (2000-09-01), Furukawa et al.
patent: 6140175 (2000-10-01), Kleinhenz et al.
patent: 6552382 (2003-04-01), Wu
patent: 6867450 (2005-03-01), Kito et al.
patent: 2-263473 (1990-10-01), None
patent: 2002-118255 (2002-04-01), None
D. Hisamoto et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.

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