Trench DRAM cell with vertical device and buried word lines

Details Trench DRAM cell with vertical device and buried word lines Trench DRAM cell with vertical device and buried word lines

2004-10-13

2009-02-10

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000

Reexamination Certificate

active

07488641

ABSTRACT:
A DRAM array having trench capacitor cells of potentially 4F2surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

REFERENCES:
patent: 4920389 (1990-04-01), Itoh
patent: 5001526 (1991-03-01), Gotou
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5181089 (1993-01-01), Matsuo et al.
patent: 5252845 (1993-10-01), Kim et al.
patent: 5302541 (1994-04-01), Akazawa
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5334548 (1994-08-01), Shen et al.
patent: 5346834 (1994-09-01), Hisamoto et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5561307 (1996-10-01), Mihara et al.
patent: 5581101 (1996-12-01), Ning et al.
patent: 5677227 (1997-10-01), Yang et al.
patent: 5753947 (1998-05-01), Gonzalez
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5963469 (1999-10-01), Forbes
patent: 5977579 (1999-11-01), Noble
patent: 6008104 (1999-12-01), Schrems
patent: 6072209 (2000-06-01), Noble et al.
patent: 6091094 (2000-07-01), Rupp
patent: 6150210 (2000-11-01), Arnold
patent: 6150320 (2000-11-01), Arnold
patent: 6150687 (2000-11-01), Noble et al.
patent: 6191470 (2001-02-01), Forbes et al.
patent: 6395597 (2002-05-01), Noble
patent: 6498062 (2002-12-01), Durcan et al.
patent: 6624033 (2003-09-01), Noble
patent: 6696746 (2004-02-01), Farrar et al.
patent: 6844591 (2005-01-01), Tran
patent: 6946700 (2005-09-01), Noble
patent: 7071043 (2006-07-01), Tang et al.
patent: 7122425 (2006-10-01), Chance et al.
patent: 7214621 (2007-05-01), Nejad et al.
patent: 7244659 (2007-07-01), Tang et al.
patent: 7262089 (2007-08-01), Abbott et al.
patent: 7282401 (2007-10-01), Juengling
patent: 7285812 (2007-10-01), Tang et al.
patent: 7349232 (2008-03-01), Wang et al.
patent: 7384849 (2008-06-01), Parekh et al.
patent: 315803 (1989-05-01), None
patent: 63260166 (1988-10-01), None
W. F. Richardson et al, “A Trench Transistor Cross-Point DRAM Cell”, 1985 IEEE, pp. 714-717.
Hyun-Jin Cho et al, “A Novel Pillar DRAM Cell for 4Gbit and Beyond”, 1998 symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
C. J. Radens et al., “A 0.21μm27F2Trench Cell With A Locally-Open Globally-Folded Dual Bitline For 1Gb/4Gb DRAM”, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 36-37.

Affiliated with

Also associated with

Rating

Trench DRAM cell with vertical device and buried word lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trench DRAM cell with vertical device and buried word lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench DRAM cell with vertical device and buried word lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4109332