Trench DRAM cell with vertical device and buried word lines

Details Trench DRAM cell with vertical device and buried word lines Trench DRAM cell with vertical device and buried word lines

1999-09-27

2002-05-28

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S244000, C438S269000

Reexamination Certificate

active

06395597

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to an improved semiconductor structure for high density device arrays, and in particular to a trench DRAM cell array, and to a process for its formation.
BACKGROUND OF THE INVENTION
There are two major types of random-access memory cells, dynamic and static. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. Static random-access memories are so named because they do not require periodic refreshing.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
42
. For each cell, the capacitor
44
has two connections, located on opposite sides of the capacitor
44
. The first connection is to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The second connection is to the drain of the FET
46
. The gate of the FET
46
is connected to the word line
48
, and the source of the FET is connected to the bit line
50
. This connection enables the word line
48
to control access to the capacitor
44
by allowing or preventing a signal (a logic “0” or a logic “1”) on the bit line
50
to be written to or read from the capacitor
44
.
The body of the FET
46
is connected to the body line
76
, which is used to apply a fixed potential to the body. Body lines are used to avoid floating body threshold voltage instabilities that occur when FETs are used on silicon-on-insulator (SOI) substrates. These threshold voltage instabilities occur because the body of the FET does not have a fixed potential. Threshold voltage is a function of the potential difference between the source and the body of a FET, so if the body does not have a fixed potential, then the threshold voltage will be unstable. Because control of the threshold voltage is especially critical in DRAM cells, a body line may be used to provide the body of the FET with a fixed potential so that the threshold voltage of the FET may thereby be stabilized.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices.
Conventional folded bit line cells of the 256 Mbit generation with planar devices have a size of at least 8F
2
, where F is the minimum lithographic feature size. If a folded bit line is not used, the cell may be reduced to 6 or 7 F
2
. To achieve a smaller size, vertical devices must be used. Cell sizes of 4F
2
may be achieved by using vertical transistors stacked either below or above the cell capacitors, as in the “cross-point cell” of W. F. Richardson et al., “A Trench Transistor Cross-Point DRAM Cell,” IEDM Technical Digest, pp. 714-17 (1985). Known cross-point cells, which have a memory cell located at the intersection of each bit line and each word line, are expensive and difficult to fabricate because the structure of the array devices is typically incompatible with that of non-array devices. Other known vertical cell DRAMs using stacked capacitors have integration problems due to the extreme topography of the capacitors.
There is needed, therefore, a DRAM cell having an area of 4F
2
or smaller that achieves high array density while maintaining structural commonality between array and peripheral (non-array) features. Also needed is a simple method of fabricating a trench DRAM cell that maximizes common process steps during the formation of array and peripheral devices.
SUMMARY OF THE INVENTION
The present invention provides a DRAM cell array having a cell area of 4F
2
or smaller which comprises an array of vertical transistors located over an array of trench capacitors. The trench capacitor for each cell is located beneath and to one side of the vertical transistor, thereby decreasing the cell area while maintaining compatibility of the vertical transistors with peripheral devices. Also provided is a simplified process for fabricating the DRAM cell array which may share common process steps with peripheral device formation so as to minimize the fabrication cost of the array.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.


REFERENCES:
patent: 5001526 (1991-03-01), Gotou
patent: 5252845 (1993-10-01), Kim et al.
patent: 5302541 (1994-04-01), Akazawa
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5334548 (1994-08-01), Shen et al.
patent: 5346834 (1994-09-01), Hisamoto et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5753947 (1998-05-01), Gonzalez
patent: 6008104 (1999-12-01), Schrems
patent: 6091094 (2000-07-01), Rupp
patent: 6150210 (2000-11-01), Arnold
W. F. Richardson et al, “A Trench Transistor Cross-Point DRAM Cell”, 1985 IEEE, pp. 714-717.
Hyun-Jin Cho et al, “A Novel Pillar DRAM Cell for 4Gbit and Beyond”, 1998 symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
C. J. Radens et al., “A 0.21&mgr;m27F2Trench Cell with a Locally-Open Globally-Folded Dual Bitline for 1Gb/4Gb DRAM”, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 36-37.

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