Trench DMOS transistor with embedded trench schottky rectifier

Details Trench DMOS transistor with embedded trench schottky rectifier Trench DMOS transistor with embedded trench schottky rectifier

2003-05-30

2004-07-13

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S576000, C257S335000, C257S476000

Reexamination Certificate

active

06762098

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits comprising power MOSFETs in parallel with Schottky barrier rectifiers. More particularly, the present invention relates to the integration of trench DMOSFETs and trench Schottky rectifiers upon a single substrate.
BACKGROUND OF THE INVENTION
Schottky barrier rectifiers (also referred to as Schottky barrier diodes) have been used as synchronous rectifiers in DC—DC power converters. An improved version of a Schottky barrier rectifier is disclosed in U.S. Pat. No. 5,365,102 entitled “Schottky Barrier Rectifier with MOS Trench.” A cross-sectional view of such a device is illustrated in FIG.
1
. In this figure, rectifier
10
includes a semiconductor substrate
12
of first conductivity type, typically N-type conductivity, having a first face
12
a
and a second opposing face
12
b
. The substrate
12
comprises a relatively highly doped cathode region
12
c
(shown as N+) adjacent the first face
12
a
. A drift region
12
d
of first conductivity type (shown as N) extends from the cathode region
12
c
to the second face
12
b
. Hence, the doping concentration of the cathode region
12
c
is greater than that of the drift region
12
d
. A mesa
14
having a cross-sectional width “Wm”, defined by opposing sides
14
a
and
14
b
, is formed in the drift region
12
d
. The mesa can be of stripe, rectangular, cylindrical or other similar geometry. Insulating regions
16
a
and
16
b
(e.g., SiO
2
) are also provided on the mesa sides. The rectifier also includes an anode electrode
18
on the insulating regions
16
a
,
16
b
. The anode electrode
18
forms a Schottky rectifying contact with the mesa
14
. The height of the Schottky barrier formed at the anode electrode/mesa interface is dependent not only on the type of electrode metal and semiconductor (e.g., Si, Ge, GaAs, and SiC) used, but is also dependent on the doping concentration in the mesa
14
. A cathode electrode
20
is provided adjacent the cathode region
12
c
at the first face
12
a
. The cathode electrode
20
ohmically contacts cathode region
12
c
. Such a trench MOS Schottky barrier rectifier displays significant improvements in reverse blocking voltage. Typically, two or more individual trench MOS Schottky barrier rectifiers are fabricated in parallel, with rectifiers sharing common anode and cathode contacts. As a result, the individual trench MOS Schottky barrier rectifiers act as a single rectifier.
Unfortunately, Schottky barrier rectifiers, including those described in U.S. Pat. No. 5,365,102, have relatively high on-resistance (forward-biased voltage drop). Moreover, many Schottky barrier rectifiers have relatively high reverse-biased leakage currents. As a result, Schottky barrier rectifiers are frequently replaced for power conversion applications by power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which address these problems.
DMOS transistors (Double diffused MOSFETs) (also referred to herein as DMOSFETs) are a type of MOSFET that use diffusion to form the transistor regions. A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.
One particular type of DMOS transistor is a “trench DMOS transistor” in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance (forward-biased voltage drop). Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
FIGS. 2
a
-
2
C illustrate one embodiment of a conventional trench DMOS structure
120
in which the individual cells
121
are rectangular in shape in a horizontal cross-section. It should be noted that the transistor cells
121
need not have a rectangular shape for basic transistor operation, but more generally may have any polygonal shape. However, a regular rectangular shape and a regular hexagonal shape are generally considered most convenient for layout purposes. The structure includes, in this embodiment, an N+ substrate
100
on which is grown a lightly n-doped epitaxial layer
104
. Within doped epitaxial layer
104
, a body region
116
of opposite conductivity is provided. An n-doped epitaxial layer
140
that overlies much of the body region
116
serves as the source. A rectangularly shaped trench
124
is provided in the epitaxial layers, which is open at the upper surface of the structure and defines the perimeter of the transistor cell. A gate oxide layer
130
lines the bottom and sidewalls of the trench
124
. The trench
124
is filled with polysilicon, i.e., polycrystalline silicon. A drain electrode is connected to the back surface of the semiconductor substrate
100
, a source electrode
118
is connected to the source regions
140
and the body region
116
, and a gate electrode is connected to the polysilicon that fills the trench
124
. As seen in
FIG. 2A
, the polysilicon lining trenches
124
is continuously connected over the surface of structure
120
. In addition, polysilicon contacts
129
extend beyond the surface of structure
120
to serve as interconnects. It should be noted that, rather than having a closed-cell geometry as depicted in the figures, the transistor cell may have an open or stripe geometry.
As indicated, the DMOS transistor shown in
FIGS. 2A-C
has its gate positioned in a vertically oriented trench. This structure is often called a trench vertical DMOS. It is “vertical” because the drain contact appears on the back or underside of the substrate and because the channel flow of current from source to drain is approximately vertical. This minimizes the higher resistance associated with bent or curved current paths or with parasitic field effect construction. The device is also doubly diffused (denoted by the prefix “D”) because the source region is diffused into the epitaxial material on top of a portion of the earlier-diffused body region of opposite conductivity type. This structure uses the trench sidewall area for current control by the gate and has a substantially vertical current flow associated with it. As previously mentioned, this device is particularly appropriate for use as a power switching transistor where the current carried through a given transverse silicon area is to be maximized.
Unfortunately, power MOSFETs, including trench DMOS transistors, experience reduced switching speeds due to the long recovery time of the built-in body diode, rendering them less than ideal for high frequency applications.
This problem has been addressed in the art by combining a power MOSFET in parallel with a Schottky barrier rectifier as demonstrated in
FIGS. 3A through 3F
.
A portion of a prior art trench DMOS transistor is illustrated schematically in FIG.
3
A. Such a transistor behaves as if having a built-in body diode D
b
as shown in FIG.
3
A. When provided within a circuit, the transistor shown in
FIG. 3A
can be illustrated as the portion of
FIG. 3B
surrounded by the dashed lines. The built-in body diode is represented by D
2
in
FIG. 3B
, which also contains switch S
2
associated with the transistor. Also shown in the circuit of
FIG. 3B
are switch S
1
and diode D
1
, as well as inductor L
1
, capacitor C
1
and load R
1
. A voltage V
in
is applied across the circuit as shown.
FIG. 3C
illustrates two control signals, a first gate drive signal GDS
1
for driving switch S
1
and a second gate drive signal GDS
2
for driving switch S
2
, at times T
1
, T
2
, T
3
, T
4
, and T
5
. As illustrated in
FIG. 3B
, at time T
1

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