Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-01
2002-08-13
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S269000, C438S272000, C438S273000, C438S274000, C257S330000, C257S336000
Reexamination Certificate
active
06432775
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
BACKGROUND OF THE INVENTION
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use two sequential diffusion steps aligned to the same edge to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage, high current devices for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
One example is the low voltage prior art trenched DMOS transistor shown in the cross-sectional view of FIG.
1
. As shown in
FIG. 1
, trenched DMOS transistor
10
includes heavily doped substrate
11
, upon which is formed an epitaxial layer
12
, which is more lightly doped than substrate
11
. Metallic layer
13
is formed on the bottom of substrate
11
, allowing an electrical contact
14
to be made to substrate
11
. As is known to those of ordinary skill in the art, DMOS transistors also include source regions
16
a
,
16
b
,
16
c
, and
16
d
, and body regions
15
a
and
15
b
. Epitaxial region
12
serves as the drain. In the example shown in
FIG. 1
, substrate
11
is relatively highly doped with N-type dopants, epitaxial layer
12
is relatively lightly doped with N type dopants, source regions
16
a
,
16
b
,
16
c
, and
16
d
are relatively highly doped with N type dopants, and body regions
15
a
and
15
b
are relatively highly doped with P type dopants. Doped polycrystalline silicon
18
is formed within a trench, and is electrically insulated from other regions by gate dielectric layer
17
formed on the bottom and sides of the trench. The trench extends into the heavily doped substrate
11
to reduce any resistance caused by the flow of carriers through the lightly doped epitaxial layer
12
, but this structure also limits the drain-to-source breakdown voltage of the transistor. A drain electrode
14
is connected to the back surface of the substrate
11
, a source electrode
22
is connected to the source regions
16
and the body regions
15
through metallic contact layer
20
, and a gate electrode
19
is connected to the polysilicon
18
that fills the trench.
Another example of a trenched DMOS device is disclosed in U.S. Pat. No. 4,893,160 and shown in the cross-sectional view of FIG.
2
. As shown in
FIG. 2
, trenched DMOS device
30
includes metallic substrate electrode
13
, substrate
11
, epitaxial region
12
, body regions
15
a
and
15
b
, source regions
16
a
,
16
b
,
16
c
, and
16
d
, photoresist layer
35
, trench extension
38
and gate oxide
40
. However, in comparison to the device shown in
FIG. 1
, N+region
39
is added along the lower sides and bottom of trench
36
, or alternatively just along the bottom of trench
36
. This structure improves the device performance by allowing carriers to flow through a heavily doped region at the bottom of the trench, thereby reducing the local resistance.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region. A source region is formed on the surface of the first semiconductor region and a body region is formed within the first region beneath the source region. The body region has a second conductivity type opposite to the first conductivity type.
REFERENCES:
patent: 5877528 (1999-03-01), So
Fahmy Wael
General Semiconductor Inc.
Lee Hsien-Ming
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
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