Trench DMOS transistor having a double gate structure

Details Trench DMOS transistor having a double gate structure Trench DMOS transistor having a double gate structure

2001-06-01

2003-02-11

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S242000, C438S259000, C257S329000, C257S330000

Reexamination Certificate

active

06518127

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
BACKGROUND OF THE INVENTION
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use two sequential diffusion steps aligned to the same edge to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage, high current devices for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate. While the individual DMOS transistor cells are typically rectangular in shape, they can in general have an open or closed cell geometry.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
One example is the low voltage prior art trenched DMOS transistor shown in the cross-sectional view of FIG.
1
. As shown in
FIG. 1
, trenched DMOS transistor
10
includes heavily doped substrate
11
, upon which is formed an epitaxial layer
12
, which is more lightly doped than substrate
11
. Metallic layer
13
is formed on the bottom of substrate
11
, allowing an electrical contact
14
to be made to substrate
11
. As is known to those of ordinary skill in the art, DMOS transistors also include source regions
16
a
,
16
b
,
16
c
, and
16
d
, and body regions
15
a
and
15
b
. Epitaxial region
12
serves as the drain. Substrate
11
is relatively highly doped with N-type dopants, epitaxial layer
12
is relatively lightly doped with N type dopants, source regions
16
a
,
16
b
,
16
c
, and
16
d
are relatively highly doped with N type dopants, and body regions
15
a
and
15
b
are relatively highly doped with P type dopants. A doped polycrystalline silicon gate electrode
18
is formed within a trench, and is electrically insulated from other regions by gate dielectric layer
17
formed on the bottom and sides of the trench containing gate electrode
18
. The trench extends into the heavily doped substrate
11
to reduce any resistance caused by the flow of carriers through the lightly doped epitaxial layer
12
, but this structure also limits the drain-to-source breakdown voltage of the transistor. A drain electrode
14
is connected to the back surface of the substrate
11
, a source electrode
22
is connected to the source regions
16
and the body regions
15
, and a gate electrode
19
is connected to the polysilicon
18
that fills the trench.
In the DMOS transistor shown in
FIG. 1
there is a trade-off between the device's on-resistance and its drain-to-source breakdown voltage. As the depth of the trench increases, the on-resistance decreases because an accumulation layer forms along the side-wall of the trench. However, the drain-to-source breakdown voltage decreases with increasing trench depth. This latter trend occurs because the depletion layer extending along the trench upon application of a reverse bias voltage cannot spread as the distance between the substrate and the bottom of the trench decreases. As a result, the electric field is concentrated at the bottom corner of the trench and thus breakdown occurs at this point. While the electric field can be reduced by increasing the thickness of the gate oxide layer lining the trench, this adversely effects the on-resistance of the device.
Y. Baba et al., in Proc. of ISPSD & IC, p300, 1992, discloses a trench DMOS transistor having a relatively low on-resistance and a high drain-to-source breakdown voltage. A transistor with such characteristics is accomplished by providing a double gate oxide structure that has a thicker gate oxide layer at the bottom of the trench and a thinner gate oxide layer along the side-walls of the upper portion of the trench. This arrangement provides a more optimal trade-off between the device's on-resistance and its drain-to-source breakdown voltage. Specifically, while the trench is sufficiently deep so that the on-resistance of the device is adequately low, the thickness of the gate oxide region is increased where it can most effectively reduce the electric field at the bottom of the trench; however, the remainder of the gate oxide layer has a reduced thickness so that the on-resistance is minimally impacted.
One limitation of the trench DMOS transistor shown in the previously mentioned reference is that it can be difficult to produce the double gate oxide structure, particularly at high transistor cell densities when the width of the trench becomes narrow. Another limitation of the device shown in
FIG. 1
is that at high switching speeds its switching losses are relatively large because of its gate charge, which leads to increased capacitance.
Accordingly, it would be desirable to provide a trench DMOS transistor having a double gate oxide structure that is relatively simple to manufacture, particularly at high trench cell densities when the trench is narrow and which has a reduced gate charge to reduce switching losses.
SUMMARY OF THE INVENTION
In accordance with the present invention, a trench DMOS transistor cell is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.
In accordance with one aspect of the invention, the interface is located at a depth between an upper and lower boundary of the body region.
In accordance with another aspect of the invention, the conductive electrode is formed from polysilicon. Alternatively, the conductive electrode may be formed in whole or in part from silicide.
In accordance with yet another aspect of the invention, the insulating layer is an oxide layer.
In accordance with another aspect of the invention, a trench DMOS transistor structure is provided, which includes a plurality of individual trench DMOS transistor cells formed on a substrate of a first conductivity type. Each of the individual trench DMOS transistor cells include a body region, which has a second conductivity type, located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulatin

Affiliated with

Also associated with

Rating

Trench DMOS transistor having a double gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trench DMOS transistor having a double gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench DMOS transistor having a double gate structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3137990