Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-30
2003-12-02
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S331000, C257S329000
Reexamination Certificate
active
06657255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to trench DMOS devices, and more particularly to trench DMOS devices with improved contact features.
BACKGROUND OF THE INVENTION
A DMOS (Double Diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses diffusion to form the transistor region. DMOS transistors are typically employed as power transistors for high voltage power integrated circuits. DMOS transistors provide high current per unit area where low forward voltage drops are required.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon (i.e., polycrystalline silicon), allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931, the disclosures of which are hereby incorporated by reference.
FIG. 1
illustrates half of a hexagonally shaped prior art trench DMOS structure
21
. The structure includes an n+ substrate
23
, upon which is grown a lightly doped n epitaxial layer
25
of a predetermined depth depi. Within the epi layer
25
, p body region
27
(p, p+) is provided. In the design shown, the p body region
27
is substantially planar (except in a central region), lying a distance dmin below the top surface of the epi layer. Another layer
28
(n+) overlying most of the p body region
27
serves as source. A series of hexagonally shaped trenches
29
are provided in the epitaxial layer, opening toward the top and having a predetermined depth dtr. The trenches
29
are typically lined with oxide and filled with conductive polysilicon, forming the gate for the DMOS device. The trenches
29
define cell regions
31
that are also hexagonally shaped in horizontal cross-section. Within the cell region
31
, the p body region
27
rises to the top surface of the epi layer and forms an exposed pattern
33
in a horizontal cross section at the top surface of the cell region
31
. In the specific design illustrated, the p+ central portion of the p body region
27
extends to a depth dmax below the surface of the epi layer that is greater than the trench depth dtr for the transistor cell so that breakdown voltage is away from the trench surface and into the bulk of the semiconductor material.
A typical DMOS device includes numerous individual DMOS transistor cells
31
that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, the chip shown in
FIG. 1
contains numerous hexagonal-shaped cells
31
(portions of five of these cells are illustrated). Cell configurations other than hexagonal configurations are commonly used, including square-shaped configurations. In a design like that shown in
FIG. 1
, the substrate region
23
acts as a common drain for all of the individual DMOS transistor cells
31
. Although not illustrated, all the sources for the DMOS cells
31
are typically shorted together via a metal source contact that is disposed on top of the n+ source regions
28
. An insulating region, such as borophosphosilicate glass (not shown) is typically placed between the polysilicon in the trenches
29
and the metal source contact to prevent the gate regions from being shorted with the source regions. Consequently, to make gate contact, the polysilicon within the trenches
29
is typically extended into a termination region beyond the DMOS cells
31
, where a metal gate contact is provided on the polysilicon. Since the polysilicon gate regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells
31
, these cells
31
behave as a single large transistor.
Unfortunately, in a prior art design like that described above, contact with the drain is made from the underside of the chip, while source and gate contact is made from the topside of the chip. As a result, it is typically necessary to dispose the chip within a package that provides source, drain and gate contacts on a single surface.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a trench DMOS transistor device is provided that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) a low resistivity deep region extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device.
Preferably, the low resistivity deep region has a resistivity of 0.01 Ohm-cm or less, extending at least 20% of the distance from the upper surface of the epitaxial layer to the substrate, and more preferably all the way to the substrate.
The deep region can comprise, for example, a doped region of first conductivity type within the epitaxial layer, a metallic region (such as aluminum), or a doped polysilicon region.
Preferably, the trench DMOS transistor device includes a plurality of transistor cells (typically of square-shaped or hexagonal geometry), which is preferably provided with a common source contact, a common drain contact and a common gate contact, each provided on a top surface of the device.
According to another embodiment of the invention, a trench DMOS transistor device is provided that comprises: (a) a silicon substrate of N-type conductivity; (b) a silicon epitaxial layer of the N-type conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) a silicon oxide insulating layer lining at least a portion of the trench; (e) a doped polycrystalline silicon conductive region within the trench adjacent the insulating layer; (f) a body region of P-type conductivity provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of N-type conductivity provided within an upper portion of the body region and adjacent the trench; and (h) a low resistivity deep region extending from an upper surface of the epitaxial layer to the substrate, which is a common drain region for the device.
According to another embodiment of the invention, a method of forming a trench DMOS transistor device is provided. The method comprises: (a) providing a substrate of a first conductivity type; (b) depositing an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) forming a body region of a second conductivity type within an upper portion of the epitaxial layer; (d) etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (e) forming an insulating layer lining at least a portion of the trench; (f) forming a conductive region within the trench adjacent the insulating layer; (g) forming a source region of the first conductivity type within an upper portion of the body region and adjacent the trench; and (h) forming a low resistivity deep region extending into the d
Amato John E.
Hshieh Fwu-Iuan
Nelson William John
So Koon Chong
Bonham, Esq. David B.
Cao Phat X.
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Williams Esq. Karin L.
LandOfFree
Trench DMOS device with improved drain contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Trench DMOS device with improved drain contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench DMOS device with improved drain contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3102658