Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-27
2001-02-13
Whitehead, Jr., Carl (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S333000, C257S335000, C257S328000, C257S374000, C257S397000, C257S520000, C257S619000, C257S622000, C257S060000, C257S127000, C257S170000
Reexamination Certificate
active
06188104
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a TDMOS (Trench Double Diffused MOS or trench DMOS) device with a trench gate structure capable of reducing a leakage current thereof and improving an insulation characteristic of a gate oxide layer, and a method for fabricating the same.
BACKGROUND OF THE INVENTION
In a typical TDMOS device with a trench gate structure, a gate oxide layer is formed on the bottom and sidewalls of the trench, and a channel region between source and drain is formed on the sidewalls of the trench. A current flowing between the source and drain flows vertically along the sidewalls of the trench.
In this TDMOS device, if the trench is not formed with a smoothed shape at the bottom edges, or if the trench is formed having a vertical shape thereat, electric field can be concentrated there, and thereby a leakage current of the gate oxide layer is increased. As a result, the insulation characteristic of the gate oxide layer is deteriorated disproportionately.
It is difficult to fabricate a trench having a smoothed shape at an edge of bottom. A technique for addressing this problem has been disclosed in the invention entitled “TRENCH GATE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR” in U.S. Pat. No. 5,142,640.
Also, since the trench has a vertical shape even at the top edges thereof, the above-mentioned problem is caused. A technique for addressing this problem has been disclosed in the invention entitled “METHOD FOR FORMING CAPACITOR IN TRENCH OF SEMICONDUCTOR WAFER BY IMPLANTATION OF TRENCH SURFACE WITH OXYGEN” to Levy in U.S. Pat. No. 5,183,775 published in Feb. 2, 1993.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved trench DMOS device which is capable of reducing a leakage current in a trench gate structure thereof, and a method for fabricating the same.
It is another object of the present invention to provide an improved trench DMOS device which is capable of improving an insulation characteristic of a gate oxide layer thereof, and a method for fabricating the same.
According to a first embodiment of the invention, there is provided a trench DMOS device comprising a semiconductor substrate having a trench therein. A gate insulating layer is formed on the bottom and sidewalls of the trench. A first conductive layer is formed on the gate insulating layer, and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer. Accordingly the first conductive layer acts as a buffer between the gate insulating layer and the filled in second conductive layer. As a result, the gate insulating layer is less susceptible to distortion due to changes of grain of the second conductive layer.
According to a second embodiment, a trench DMOS device has a round shaped structure at the upper edges of the trench. This prevents the electric field from being concentrated in the gate oxide layer at the upper edges of the trench.
According to a third embodiment, a trench DMOS device has the features of both the first and second embodiments. Specifically, a conductive layer buffers the gate oxide layer from the filled in conductive layer, and the upper edges of the trench are rounded.
A method is provided according to the present invention for fabricating a trench DMOS device. The method comprises the steps of preparing a semiconductor substrate of a first conductivity type, and then forming on it an epitaxial layer of a second conductivity type that has a guard ring at a bottom thereof. Then an impurity is injected into the epitaxial layer to form an impurity injection region of the first conductivity type. Then a first and a second insulating layers are formed sequentially over the epitaxial layer. The second insulating layer is patterned to form a pattern. Then the first insulating layer and the epitaxial layer are etched sequentially using the pattern as a mask, to form a trench in the semiconductor substrate passing through the impurity injection region. Then a dry etching process is used to round the upper edges of the trench. Then a third insulating layer is formed on the bottom and the sidewalls of the trench. Then a first conductive layer is formed on the third insulating layer and a second conductive layer is formed on the first conductive layer and filled in the trench. The second conductive layer has different crystallization from the first conductive layer.
REFERENCES:
patent: 5341011 (1994-08-01), Hshieh et al.
patent: 5342792 (1994-08-01), Yonehara
patent: 5656843 (1997-08-01), Goodyear et al.
patent: 5843819 (1998-12-01), Kellner et al.
patent: 5910669 (1999-06-01), Change et al.
patent: 5915180 (1999-06-01), Hara et al.
patent: 5929481 (1999-07-01), Hshieh et al.
Choi Mun-Heui
Jeong Dong-Soo
Jr. Carl Whitehead
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd
Warren Matthew E.
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