Trench capacitor with hybrid surface orientation substrate

Details Trench capacitor with hybrid surface orientation substrate Trench capacitor with hybrid surface orientation substrate

2007-06-12

2007-06-12

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S245000, C257SE21651

Reexamination Certificate

active

10904583

ABSTRACT:
Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

REFERENCES:
patent: 6037208 (2000-03-01), Wei
patent: 6544837 (2003-04-01), Divakauni et al.
patent: 6555891 (2003-04-01), Furukawa et al.
patent: 6635543 (2003-10-01), Furukawa et al.
patent: 2004/0002233 (2004-01-01), Advocate, Jr. et al.
Yang, M. et al., “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations,” IEEE International Electron Devices Meeting, Dec. 8-10, 2003.

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