Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-12
2004-02-17
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S173000, C438S206000, C438S268000, C438S386000
Reexamination Certificate
active
06693005
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a trench capacitor for use in a memory cell and a method for making the same. Particularly, the present invention relates to a trench capacitor with an expanded area for use in a memory cell and a method for making the same.
BACKGROUND OF THE INVENTION
The total storage capacitance of a trench capacitor is determined by the total active surface area of the trench capacitor. The present invention focuses on how to increase the storage capacitance by increasing the surface area of a trench capacitor.
FIG. 1
shows the structure of a conventional memory cell formed in a semiconductor substrate. Conventionally, the trench capacitor is only formed in the lower portion of a trench. The semiconductor substrate has a first well region
14
and a second well region
16
, wherein the first well region
14
is preferably a buried N-well and the second well region
16
is preferably a P-well. Although the trench is vertically extended through the first
14
and second well region
16
, the surface area of the trench capacitor can only be the sidewall at the lower portion of the trench (with a length marked “d” in FIG.
1
). Obviously, the sidewall at the upper portion has no substantial contribution to the storage capacitance.
Conventionally, as shown in
FIG. 1
, the inner sidewall of the trench is covered with a collar oxide layer
12
. The buried N-well
14
, a doped amorphous-silicon material
13
, and a source of the DRAM
15
are used as the source, gate, and drain of the vertical transistor
17
respectively. If the effective channel length (marked “m” in
FIG. 1
) of the vertical transistor
17
is reduced, a leakage current between the source of the DRAM
15
and the buried N-well
14
might easily be induced. Since the leakage current is fatal to the reliability of the memory cell, the length of the collar oxide layer
12
of the conventional trench capacitor should be kept with at least a minimum length to prevent the leakage current from being induced. Therefore, according to the conventional art, the limited length of the collar oxide layer
12
makes it hard to increase the storage capacitance of the memory cell.
It is therefore attempted by the present applicant to deal with the above situation encountered with the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel trench capacitor and a method for making the same such that the aforementioned limitations and difficulties encountered in the prior art can be overcome.
Another object of the present invention is to provide a novel trench capacitor with an expanded area for effectively increasing the storage capacitance thereof.
According to one aspect of the present invention, a method of forming a trench capacitor for use in a memory cell is provided. The method comprises steps of (a) forming a vertical trench in a semiconductor substrate, (b) filling a sacrificing material into a lower portion of the trench, (c) forming a collar isolation layer on an inner sidewall of an upper portion of said trench, (d) removing top of the sacrificing material to expose a belt of inner sidewall of the lower portion, (e) forming a doped silicon liner layer to cover the collar isolation layer and the belt of inner sidewall of the lower portion, (f) removing the sacrificing material, (g) forming a doping region around the lower portion of the trench, (h) forming a dielectric layer on all inner surface of the trench, and (i) filling a doped silicon material into the trench.
Preferably, after the step (b), the method further includes a step (b1) of etching back.
Preferably, the sacrificing material is an oxide material.
Preferably, the collar isolation layer includes a thin thermal oxide layer and a silicon nitride layer.
Preferably, the step (d) is achieved by etching back via using a hydrofluoric (HF) solution.
Preferably, after the step (e), the method further includes a step (e1) of etching back.
Preferably, the doping region is serving as an outer capacitor plate of the trench capacitor.
Preferably, the doping region is a N
+
out-diffusion area.
Preferably, the step (g) is achieved by a method selecting from arsenic glass (AsG) doping and self-aligned gas doping via outward diffusion of the arsenic ion in the trench.
Preferably, the dielectric layer is serving as a charge storage layer of the trench capacitor.
Preferably, the dielectric layer is an oxide-nitride-oxide (O/N/O) layer.
Preferably, the dielectric layer is an oxide-nitride (O/N) layer.
Preferably, the doped silicon material is serving as an inner capacitor plate of the trench capacitor.
Preferably, after the step (i), the method further includes the steps of (i1) wet etching; and (i2) filling a doped silicon material on top of the trench.
According to another aspect of the present invention, a trench capacitor for use in a memory cell is provided. The trench capacitor comprises a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.
Preferably, the doping region is serving as an outer capacitor plate of the trench capacitor.
Preferably, the doping region is a N
+
out-diffusion area.
Preferably, the collar isolation layer includes a thin thermal oxide layer and a silicon nitride layer.
Preferably, the dielectric layer is serving as a charge storage layer of the trench capacitor.
Preferably, the dielectric layer is an oxide-nitride-oxide (O/N/O) layer.
Preferably, the dielectric layer is an oxide-nitride (O/N) layer.
Preferably, the doped silicon material is serving as an inner capacitor plate of the trench capacitor.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
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patent: 5618751 (1997-04-01), Golden et al.
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patent: 6200873 (2001-03-01), Schrems et al.
patent: 6265742 (2001-07-01), Gruening et al.
patent: 6310375 (2001-10-01), Schrems
patent: 6331459 (2001-12-01), Gruening
patent: 6410391 (2002-06-01), Zelsacher
patent: 6426253 (2002-07-01), Tews et al.
patent: 19956078 (2001-05-01), None
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Luu Chuong A
Mosel Vitelic Inc.
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