Trench capacitor memory cell

Details Trench capacitor memory cell Trench capacitor memory cell

2000-09-26

2004-11-02

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S242000, C438S386000

Reexamination Certificate

active

06812091

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to integrated circuits (ICs) and, in particular, to a sub-8F
2
memory cell.
BACKGROUND OF THE INVENTION
FIG. 1
shows a 8F
2
trench capacitor DRAM cell. Such a DRAM cell is described in, for example, Nesbit et al., A 0.6 &mgr;m
2
256 Mb
Trench DRAM Cell With Self
-
Aligned Buried Strap
(
BEST
), IEDM 93-627, which is herein incorporated by reference for all purposes. As shown, the DRAM cell includes a trench capacitor
160
formed in a substrate
101
. The trench is filled with, for example, n-type doped-polysilicon (poly)
161
. The doped-poly serves as the storage electrode (also referred as a storage nodeo) of the capacitor. An n-doped buried plate
165
surrounds the lower portion of the trench. The buried plate serves as the second electrode of the capacitor. A dielectric collar
168
lines inner sidewalls in the upper portion of the trench to reduce vertical parasitic leakage around the deep trench. Typically, the collar is about 1 nm deep. A node dielectric
163
is provided in the lower portion of the trench separating the two plates of the capacitor. A buried well
170
comprising n-type dopants connects the buried plates of the DRAM cells in the array. A p-well can be located above the buried well to reduce vertical leakage.
A transistor
110
is coupled to the capacitor
150
. The transistor includes a gate
112
and diffusion regions
113
and
114
comprising n-type dopants. The gate of the transistor forms a gate conductor, serving as a wordline. The diffusion regions are referred to as the “source” and “drain.” The designation of source and drain depends on the operation of the transistor. Coupling of the transistor to the capacitor is achieved via a diffusion region
125
, which is formed by outdiffusing dopants from the storage node through a buried strap
127
.
To provide sub-8F
2
cells, sub-ground rule features are used to form, for example, the transistor of the cell. The use of sub-ground rule features results in decreasing the distance between the buried strap, creating process control issues.
For example, the outdiffusion of dopants from the buried strap to form diffusion region
125
can easily diffuse into the channel region of the transistor, which can result in shorts. The use of sub-ground rule features to form the gates also decreases channel length, which requires larger implant doses to control the gate threshold voltage (V
T
). This leads to increased junction leakage, thus decreasing performance and device reliability.
As evident from the above discussion, it is desirable to provide an improved sub-8F
2
cell memory cell.
SUMMARY OF THE INVENTION
The invention relates to an improved sub-8F
2
memory cell. The memory cell includes a trench capacitor coupled to a transistor via a buried strap. In one embodiment, the buried strap is formed after the formation of a shallow trench isolation. The strap is formed without requiring a mask. Forming the buried strap after the shallow trench isolation is formed advantageously reduces out diffusion of dopants.
In another embodiment, a shallow transistor trench is formed in the substrate in which a buried portion of the transistor occupies. The shallow transistor trench enables an increase in channel length of the transistor without increasing the surface area needed to form the transistor. In one embodiment, self-aligned capping layer is provided on top of the deep trench capacitor to serve as a mask to form the shallow transistor trench. The capping layer prevents the shallow transistor trench from cutting the buried strap connection, thereby increasing process tolerances.


REFERENCES:
patent: 5168336 (1992-12-01), Mikoshiba
patent: 6037194 (2000-03-01), Bronner et al.
patent: 1030362 (2000-08-01), None
patent: 60257655 (1985-11-01), None
patent: 62-118567 (1987-05-01), None
patent: 01008367 (1989-01-01), None
patent: 01010310 (1989-01-01), None
patent: 02-188957 (1990-07-01), None
patent: 02-189968 (1990-07-01), None

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