Trench capacitor DRAM cell using buried oxide as array top...

Details Trench capacitor DRAM cell using buried oxide as array top... Trench capacitor DRAM cell using buried oxide as array top...

2007-03-27

2007-03-27

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S242000, C438S241000, C438S244000, C438S239000, C257S301000, C257S302000, C257S303000, C257S304000

Reexamination Certificate

active

10886439

ABSTRACT:
A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.

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patent: 5770484 (1998-06-01), Kleinhenz
patent: 5959322 (1999-09-01), Lee
patent: 6399447 (2002-06-01), Clevenger et al.
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patent: 6635915 (2003-10-01), Kokubun
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patent: 6855976 (2005-02-01), Nagano et al.
patent: 6858491 (2005-02-01), Kokubun
patent: 2002/0064913 (2002-05-01), Adkisson et al.

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