Trap charge equalizing method and threshold voltage...

Details Trap charge equalizing method and threshold voltage... Trap charge equalizing method and threshold voltage...

2010-01-05

2011-11-15

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

C438S261000, C257SE21211

Reexamination Certificate

active

08058187

ABSTRACT:
A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

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patent: 1020020084879 (2002-11-01), None
patent: 1020060006119 (2006-01-01), None

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