Transparent instruction word bus memory system

Details Transparent instruction word bus memory system Transparent instruction word bus memory system

1982-06-01

1985-05-28

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, G11C 1300

Patent

active

045204640

ABSTRACT:
A memory architecture for a single chip microprocessor or microcomputer in which instruction words have a greater bit length than the data words and the need exists for additional off-chip program memory. The instruction word lines from the off-chip program memory are coupled directly into the existing columns of a matrix on-chip, program memory ROM. Supplemental FETs are connected to selected rows and columns of the on-chip ROM and are operated in such a way that it is possible to either enable the on-chip ROM and decouple the off-chip instruction words, or to disable the on-chip ROM and couple the off-chip instruction words through the on-chip ROM.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.

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