Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-05-08
1998-07-21
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
G06F 1210
Patent
active
057847088
ABSTRACT:
A computing system includes a memory bus, an input/output bus, a main memory, and an input/output adapter. The memory bus provides information transfer. The input/output bus also provides information transfer. For example the input/output bus is an input/output bus onto which is connected input/output devices. The main memory is connected to the memory bus. The main memory includes a page directory. The page directory stores translations. Each translation in the page directory includes a portion of an address for data transferred over the input/output bus, for example, the page address portion of I/O bus address. Each translation in the page directory also is indexed by a portion of an address for a memory location within the main memory, for example, the page address portion of the address for the memory location. The input/output adapter is connected to the memory bus and the input/output bus. The input/output adapter includes an input/output translation look-aside buffer. The input/output translation look-aside buffer includes a portion of the translations stored in the page directory.
REFERENCES:
patent: 4155119 (1979-05-01), De Ward et al.
patent: 4403282 (1983-09-01), Holberger et al.
patent: 4669043 (1987-05-01), Kaplinsky
patent: 5263140 (1993-11-01), Riordan
patent: 5301287 (1994-04-01), Herrell et al.
patent: 5347636 (1994-09-01), Ooi et al.
patent: 5426750 (1995-06-01), Becker et al.
David A. Patterson, John L. Hennessy, Computer Architecture A Quantitative Approach, Morgan Kauffman Publishers, Inc., San Mateo, California, 1990, pp. 466-474.
Series 10000 Technical Reference Library Vol. 6--Core System Buses and Controllers, Order No. 011725-A00, Apollo Computer, Inc. Chelmsford, MA, 2-1 through 2-16, 3-22 through 3-28.
Patent Abstracts of Japan, vol. 10, No. 298 (P-505), Oct. 9, 1986 and JP-A-61 114352 (Fujitsu Ltd.), Jun. 2, 1986.
IBM Technical Disclosure Bulletin, vol. 19 No. 1, Jun. 1976, New York, U.S., pp. 83-84, XP002001783; Anonymous: "Minimizing Input/Output Page Pinning In A Virtual Storage Data Processor. Jun. 1976".
EP-A- 0 508 577 (IBM), Oct. 14, 1992; Abstract, Col. 4, line 54-Col. 5, line 51; figure 3.
Bridges K. Monroe
Brooks Robert
Bryg William R.
Burger Stephen G.
Ziegler Michael L.
Hewlett--Packard Company
Lane Jack A.
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