Translation look-aside buffer for improving performance and...

Details Translation look-aside buffer for improving performance and... Translation look-aside buffer for improving performance and...

2006-04-04

2006-04-04

Peikari, B. James (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S200000, C711S202000, C711S203000, C711S205000, C711S207000, C711S208000, C711S128000, C711S108000

Reexamination Certificate

active

07024536

ABSTRACT:
A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2Nphysical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

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English Abstract***.
Nesimoglu et al., ▮Dual TLB Structure to Support Two Pages Sizes▮ Apr. 13, 2000, vol. 36, No. 8, pp. 705-706.

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