Transition balancing for noise reduction/Di/Dt reduction...

Details Transition balancing for noise reduction/Di/Dt reduction... Transition balancing for noise reduction/Di/Dt reduction...

2007-10-19

2010-10-26

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C375S354000

Reexamination Certificate

active

07823107

ABSTRACT:
An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

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Arsovski et al., U.S. Appl. No. 11/460,065, Office Action Communication, Jun. 23, 2009, 6 pages.
Plosila, et al., “Pipelined On-Chip Bus Architecture With Distributed Self-Timed Control,” IEEE, 2003, pp. 257-260.

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