Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-08-19
2001-07-17
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S584000, C438S902000
Reexamination Certificate
active
06261887
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of semiconductor devices, and more particularly to transistors with independently formed gate structures and method.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices include transistors, capacitors, resistors and the like. One type of transistor is complementary metal oxide semiconductor (CMOS) transistors. CMOS transistors are a pair of transistors of opposite type used together. CMOS transistors may be used for low-dissipation logic circuits and the like.
The gates of CMOS transistors are typically constructed of a neutral material and later doped to opposite types such as n-type and p-type. The neutral gate material is generally a material that will not adversely affect the performance of either type of gate. As a result, the gate material may not be particularly well suited for either type gate.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for improved complementary metal oxide semiconductor (CMOS) and other types of transistors. The present invention provides transistors with independently formed gate structures and method that substantially eliminate or reduce the disadvantages and problems associated with prior transistors.
In accordance with the present invention, a semiconductor device may be fabricated by isolating a first region of a semiconductor layer from a second region of the semiconductor layer. A first disposable gate structure of a first transistor may be formed over the first region of the semiconductor layer. A second disposable gate structure of a second, complementary transistor may be formed over the second region of the semiconductor layer. A capping layer may be formed over the first and second regions including the first and second disposable gate structures. A portion of the first and second disposable gate structures may be exposed through the capping layer. A second disposable gate cap may be formed over the exposed portion of the second disposable gate structure and at least part of the first disposable gate structure may be removed. At least part of a first gate structure of the first transistor may be formed in the place of removed part of the first disposable gate structure.
More specifically, in accordance with one embodiment of the present invention, a second gate structure of the second transistor may comprise the second disposable gate structure. In another embodiment, a first disposable gate cap may be formed over an exposed portion of the first gate structure. The second disposable gate cap over the second disposable gate structure and at least part of the second disposable gate structure may then be removed. At least part of a second gate structure of the second transistor may then be formed in the place of the removed part of the second disposable gate structure.
In one embodiment, the first gate structure of the first transistor may comprise an in-situ doped first gate body. The second gate structure of the second transistor may comprise an in-situ doped second gate body. In this embodiment, the first and second gate bodies may each comprise polysilicon material.
In accordance with another embodiment of the present invention, a first gate body of the first gate structure may comprise a first material. A second gate body of the second gate structure may comprise a second, disparate material. In this embodiment, the first and second materials may comprise disparate metals such as platinum and aluminum.
In accordance with another embodiment of the present invention, a first gate body of the first gate structure may comprise a first material. A second gate body of the second gate structure may comprise a second, disparate material. In this embodiment, the first material may comprise p-type doped noncrystalline material comprised in part of silicon or of a silicon-germanium composition. The second material may comprise aluminum.
In accordance with another embodiment of the present invention, a first gate body of the first gate structure may comprise a first material. A second gate body of the second gate structure may comprise a second, disparate material. In this embodiment, the first material remains as the original gate material and may comprise p-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition. The second material may comprise aluminum or n-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition.
In accordance with another embodiment of the present invention, a first gate body of the first gate structure may comprise a first material. A second gate body of the second gate structure may comprise a second, disparate material. In this embodiment, the first material remains as the original gate material and may comprise n-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition. The second material may comprise platinum or p-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition.
In accordance with another embodiment of the present invention, a first gate body of the first gate structure may comprise a first material. A second gate body and/or second gate dielectric of the second gate structure may comprise a second, disparate material for the gate material and/or the gate dielectric. In this embodiment, the first material remains as the original gate material and may comprise n-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition. The first gate dielectric material remains as the original gate dielectric and may comprise oxide. The second material may comprise platinum or p-type doped non-crystalline material comprised in part of silicon or of a silicon-germanium composition. The second gate dielectric material may comprise an oxide
itride composite or nitride.
Important technical advantages of the present invention include providing transistors with independently formed gate structures. In particular, gate bodies and/or dielectrics of the transistors may be independently formed. The transistors may be complementary transistors. Accordingly, the gate structure of each transistor may be formed without regard to material and/or processes of the other.
Another technical advantage of the present invention includes providing in-situ formed gate bodies for the transistors. In particular, a first gate body of a first transistor may be in-situ doped prior to formation of the second gate structure of the second transistor. The second gate structure of the second transistor may be in-situ doped while the first gate body is protectively capped. Accordingly, additional masking and doping steps need not be conducted during the fabrication process.
Still another technical advantage of the present invention includes providing in-situ doped source and drain regions for the transistors. In particular, the source and drain of one of the transistors may be insitu doped while the other complementary transistor is masked. The newly formed source and drain of the first transistor may then be masked while the source and drain of the second transistor is in-situ doped. Accordingly, the source and drains of each of the transistors may be independently formed without regard to the materials and/or processes of the other.
Yet another technical advantage of the present invention includes providing transistors having gate bodies of disparate materials. In particular, the gate body of the first transistor may be formed prior to that of the second transistor. The gate body of the second transistor may be formed while the gate body of the first tra
Booth Richard
Brady III W. James
Garner Jacqueline J.
Lattin Christopher
Teleky, Jr. Frederick J.
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