Transistors having selectively doped channel regions

Details Transistors having selectively doped channel regions Transistors having selectively doped channel regions

2002-05-22

2004-05-04

Tran, Minh-Loan (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S276000, C438S289000, C438S296000

Reexamination Certificate

active

06730555

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices and more particularly to a method of forming transistors having selectively doped channel regions.
BACKGROUND OF THE INVENTION
One of the ways in which the complexity of integrated circuits has increased over time is the combination of different types of devices on a single substrate. For example, different types of transistors may be formed on the same integrated circuit substrate in order to provide for complex functionality from the system. For example, high speed digital transistors may be formed on the same substrate as analog devices. These transistors may have different tasks to perform in the integrated system and therefore need to have different electronic characteristics in order to perform those tasks in an optimal manner. Prior techniques have used masks which shield one type of transistor during the formation of another. These masks increase the cost and complexity of the steps needed to form the integrated systems.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an integrated system and method of formation which allows for the creation of different types of transistors and devices on a single substrate without the need for additional mask steps.
In accordance with the teachings of the present invention, a method of forming different types of transistors on a single substrate is provided that substantially eliminates or reduces disadvantages and problems associated with prior techniques.
According to one embodiment of the present invention, a method for forming a plurality of transistors on a single semiconductor substrate is provided that comprises forming a plurality of active regions in the substrate having at least two conductivity types. A conductive gate layer is then formed outwardly from the active regions. A dual implant mask is then formed outwardly from the conductive gate so that it shields selected ones of the active regions and does not shield others. A through gate implant process is then performed using the dual mask so that the channel regions of some of the active regions are affected by the through gate implant and the channel regions of the active regions shielded by the through gate implant mask are not affected substantially by the through gate implant. A gate implant step is also performed using the same dual implant mask.
An important technical advantage of certain embodiments of the present invention inheres in the fact that the use of a dual implant mask allows for the creation of particular types of transistors with particular electronic characteristics and provides a gate implant step without the need for an additional mask step.


REFERENCES:
patent: 6187643 (2001-02-01), Borland
patent: 6583013 (2003-06-01), Rodder et al.
patent: 0 643 417 (1995-03-01), None

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