Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-31
2004-04-06
Niebling, John (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S279000
Reexamination Certificate
active
06716709
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly relates to methods of forming diffusion regions of varying depths in a single implantation.
BACKGROUND OF THE INVENTION
Integrated circuits having bipolar and MOS transistors formed on the same semiconductor substrate have many uses in the electronics industry and are therefore in great demand. On significant advantage of such devices is that they combine the high power and fast switching speeds of bipolar devices with the high density and low power consumption of MOS transistors. The diversity of uses for such BiCMOS devices has fueled a surge toward fabricating faster, denser and more powerful integrated BiCMOS devices by more individual device enhancing manufacturing processes.
When forming devices using a BiCMOS manufacturing process, care is taken to minimize the number of masks employed therein to lower the manufacturing costs. Therefore efforts are made as often as is practicable to integrate the use of regions typically utilized for CMOS devices as regions in a bipolar device, and vice-versa. While such integration does serve to minimize manufacturing costs, in some cases the integration causes performance tradeoffs to be made.
For example, prior art
FIG. 1
illustrates an NPN type bipolar transistor
10
fabricated using a BiCMOS type fabrication process. The transistor
10
has an n-buried layer (NBL)
12
that is formed in a lightly doped P-type substrate
14
. A p-type epi layer
16
is then grown over the NBL
12
and the substrate
14
. A deep N+ ring
18
is then formed by performing either an n-type implant or n-type thermal deposition in the epi
16
. The deep N+ ring
18
couples down to the NBL
12
to form a collector region
20
. The deep N+ ring
18
also defines therein an isolated base region
22
comprising the p-epi. The N+ region
18
may be a ring or may simply be a single region extending down to the NBL region
12
for purposes of making contact thereto. A p-type source/drain implant is then performed to define a base contact region
24
and an n-type source/drain implant is performed to form an emitter region
26
, wherein the base contact region is formed concurrently with the formation of PMOS source/drain regions elsewhere, and the emitter region is formed concurrently with NMOS source/drain regions elsewhere, respectively.
The NPN bipolar transistor
10
of prior art
FIG. 1
may be employed in various types of applications, and in some applications the transistor breakdown voltage may be an issue. For example, a collector-to-emitter breakdown voltage (BV
CEO
) of the transistor
10
relies on the base (or epi) thickness. That is, a distance
28
between a bottom of the emitter
26
and a top of the NBL
12
will have a significant impact on BV
CEO
. Although the epi region
16
is initially thick, the thickness of the epi is reduced at locations where the NBL is present due to an up-diffusion
30
of the NBL. The thin epi
16
in that region limits transistor BV
CEO
by letting the space charge region at the NBL and epi junction reach the emitter during device operation, disadvantageously resulting in a punch-through breakdown condition.
If the epi layer thickness could be increased, or the NBL thickness could be reduced, the transistor BV
CEO
can be increased. The epi and NBL thicknesses, however, are fixed uniformly across the die for the standard BiCMOS process, and thus any local adjustments thereof would require additional masks and/or processing steps. Such additional actions are disadvantageous when attempting to minimize costs in the fabrication process.
Another NPN type bipolar transistor device fabricated in a standard BiCMOS manufacturing process is illustrated in prior art
FIG. 2
, and designated at reference numeral
50
. The transistor
50
has the NBL
12
fabricated in the substrate (p-sub)
14
and the epi layer
16
is formed thereover in a manner similar to that described above. Deep N+ regions
18
are formed down to the NBL
12
and a deep n-well region
52
is formed in the p-epi
16
down to the NBL as illustrated. Concurrently, deep n-well regions are formed elsewhere on the die and are utilized for various purposes, for example, as high voltage PMOS transistors' tank region.
Once the deep n-well region
52
is formed, a shallow P-well region
54
is formed in the deep n-well to form the base region
56
. Therefore the NBL
12
, deep N+ region
18
and the deep n-well
52
together form the collector
58
of the bipolar transistor
50
. N-type and p-type source/drain implants are then performed to form the emitter region
60
and the base contact region
62
, respectively.
The bipolar transistor
50
has a poor gain, which is sometimes referred to as the transistors &bgr; or H
FE
. When using the BiCMOS process described above, the n-type source/drain region
60
which forms the emitter is quite shallow (for CMOS optimization), and the shallow p-well
54
has a high doping concentration, is rather deep, and has a slight retrograde profile for CMOS purposes, and these factors contribute to poor bipolar transistor gain. That is, a depth
64
of the heavily doped shallow p-well
54
and the shallowness of the emitter (NSD)
60
results in a depth difference (or base width)
66
that is relatively large, thereby resulting in a low gain. This is disadvantageous in transistor applications where a high gain is important or desired.
Therefore there is a need in the art for manufacturing processes and techniques that allow for an optimization of transistor parameters without additional substantial more processing steps or employing additional masking steps.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method of forming two regions concurrently via implantation in a semiconductor body such as a substrate, wherein the two regions have differing depths. The differing depths are provided by forming a mask having one opening associated with a first region that is larger than an implantation design rule while forming a second opening in the mask associated with a second region that is smaller than the design rule. Accordingly, the second region receives less dopant than the first region during a concurrent implant through both openings, and subsequent diffusion results in the second region being more shallow than the first region. Further, the present invention contemplates first and second regions occupying approximately the same device area, but having differing depths by masking the second opening of the second region into a plurality of openings that are smaller than the design rule. After implantation and diffusion, the first and second regions are approximately the same size, but have different depths.
According to one aspect of the present invention, a method of forming a bipolar transistor is disclosed. The method comprises forming a patterned buried layer by masking over a semiconductor substrate, wherein the mask has a macroscopic opening made of a plurality of microscopic openings therein. These microscopic openings are smaller than an implantation design rule. A buried layer implant is then performed through the mask, resulting in a plurality of distinct implanted regions associated with the openings.
After thermal processing, the implanted regions diffuse together to form a buried layer region that serves as a portion of the collector region for the transistor. A semiconductor layer, for example p-epi, is formed over the substrate and forms a transistor base region, while an emitter region
Haynie Sheldon
Smith Jeff
Springer Lily
Trogolo Joe R.
Lindsay, Jr. Walter
Niebling John
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