Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-30
1999-11-23
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438304, 438265, 438286, 257344, H01L 21265
Patent
active
059899670
ABSTRACT:
An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas. In an alternative embodiment, following formation of the source and drain impurity areas, the mask is removed and the oxide regions are etched to form sidewall spacers adjacent the gate conductor. Lightly doped drain implant areas are then formed self-aligned to sidewall surfaces of the gate conductor, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
REFERENCES:
patent: 5472895 (1995-12-01), Park
patent: 5578509 (1996-11-01), Fujita
patent: 5672531 (1997-09-01), Gardner et al.
patent: 5693546 (1997-12-01), Nam et al.
patent: 5710450 (1998-01-01), Chau et al.
patent: 5783473 (1998-06-01), Sung
Stanley Wolf Silicon Processing for the VSLI Era vol. I Lattice Press pp. 182,191,192, 1986.
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Blum David S
Bowers Charles
Daffer Kevin L.
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