Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-13
2004-06-08
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C438S303000, C438S514000, C438S527000
Reexamination Certificate
active
06746906
ABSTRACT:
BACKGROUND OF THE INVENTION
Technology scaling has been a main driving force behind the rapid advancement of the semiconductor industry. As part of the scaling efforts, state of the art processes for manufacturing smaller and higher performance transistors are continuously under development. For example, it is desirable to reduce the channel length of a transistor in order to increase the current capability of the transistor and to make the overall transistor size smaller. However, in scaling down the channel length, such barriers as junction breakdown and transistor punch through must first be overcome. Junction breakdown occurs when the electric field across a reverse biased junction becomes high enough to initiate avalanche impact ionization generation, resulting in a sharp current increase. In MOS technology, the junction breakdown voltage can be improved by reducing channel doping concentration and/or using lightly doped drain (LDD) and double doped drain (DDD) junctions.
Transistor punch through is defined as the drain voltage at which the drain depletion region extends all the way to that of the source region so that the source and drain regions become electrically shorted together. The transistor thus draws an undesirably high amount of current, resulting in prohibitively high leakage current or even the destruction of the transistor. The shorter the channel length is made, the lower is the drain voltage at which the drain to source punch through occurs. This can severely limit the operational voltages of integrated circuits. In order to improve punch-through effects, the channel doping concentration may be increased; however, this in turn leads to a lower junction breakdown voltage.
One of the factors influencing the extent to which the drawn gate feature or gate line width can be scaled is the amount of the gate overlap with the source/drain (S/D) regions that a process can tolerate. Clearly, the smaller the overlap, the smaller can the gate feature be made. Achieving a small overlap is a difficult task because of the inherent side diffusion of the source and drain regions during S/D implant activation and anneal.
This limitation on scaling of MOS transistors is even more pronounced in scaling of non-volatile memory cells. This is because such features of the non-volatile memory cell as the floating gate tunnel oxide and the interpoly dielectric layer (e.g., oxide-nitride-oxide (ONO) multilayer) are not readily scalable due to quality considerations of these insulating materials and the cell charge retention constraints.
As an example, a simplified conventional process sequence for a stack gate flash memory cell includes: forming a tunnel oxide over a substrate; forming a floating gate (poly 1) over the tunnel oxide; forming an interpoly ONO dielectric composite layer; and forming a control gate (poly 2 and tungsten silicide) over the ONO dielectric. In modern technologies, the control gate is often formed simultaneously with the gates of peripheral (CMOS) transistors, followed by cell self-aligned etch (SAE) of poly 1 using poly 2 as a mask. After formation of the polysilicon stack, a re-oxidation thermal cycle is performed. In subsequent steps, DDD implanting steps are performed for periphery high voltage (HV) NMOS and PMOS transistors, followed by oxidation and anneal cycles.
Next, the cell S/D implant (in case of symmetrical S/D cells) is performed followed by forming oxide spacers along the side-walls of both the cell polysilicon stack the periphery transistor gates. The properties and physical characteristics of the source and drain regions are dependent on the thickness of the screen oxide (i.e., oxide previously deposited covering the substrate surface areas where the source and drain regions are formed) through which the S/D implant is performed, the implant dose and energy, and the thermal activation. The room for optimizing the source and drain regions is limited. The S/D implant dose has to be sufficiently high to ensure low source and drain resistance, and the implant energy needs to be optimized based on the screen oxide thickness and the junction vertical depth requirements. The above parameters along with the thermal budget of S/D activation/anneal determine the extent of the overlap between the poly stack and the S/D regions, and thus the minimum effective channel length.
As indicated earlier, scaling of the thickness of the tunnel oxide and ONO dielectric layers are substantially limited. To reduce the gate length without scaling down the tunnel oxide and the ONO dielectric layers requires formation of sufficiently deep S/D junctions (e.g., junction depth of 0.07-0.1 &mgr;m for gate length of 0.15-0.20 &mgr;m) to ensure proper functioning of the cell. Sufficient junction depth is needed for lowering source/drain resistance, and achieving the desired overlap with the gate. The gate overlap should be sufficient for proper programming, read efficiency, and reliability considerations, yet small enough to provide for sufficient effective channel length, especially for very short gate feature. As such, the lateral junction depth, and thus the overlap between the polysilicon stack and the S/D regions are predetermined and limited by the S/D implant and thermal activation requirements.
For drawn gate length of 0.2 &mgr;m, and maybe even 0.15 &mgr;m, the effective channel length (which equals the drawn gate length minus the overlaps between the gate and the S/D regions) may be sufficient for proper functioning of the cell (i.e., without punch-through and with high enough junction breakdown voltage BVdss), provided the channel doping is properly optimized. However, for gate length of about 0.12 &mgr;m and shorter, the effective channel length becomes too short, or practically disappears. The cell will exhibit punch-through at very low drain voltage, preventing the cell from proper functioning.
Even highly advanced flash technologies with memory cell gate length of 0.1 &mgr;m or shorter, require a drain voltage of 3-5V to ensure sufficient programming speed by channel hot electron injection. However, for such small gate features and voltage requirements, the above-mentioned adverse short channel effects can not be properly addressed only by optimizing the source/drain implant conditions and channel doping.
SUMMARY OF THE INVENTION
In accordance with the present invention, an off-set spacer is introduced in the process steps for manufacturing memory cells and transistors and the resulting structures which enables dramatic scaling of the channel length such that high performance transistors and memory cell structures with extremely small gate feature and overall size that exhibit robust program/erase efficiency and read speed, and enable low operating voltages, can be manufactured.
In one embodiment, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.
In another embodiment, said gate electrode forming act includes forming a gate electrode for each of first and second transistors, and said off-set spacers forming act includes forming off-set spacers along side-walls of the gate electrodes of the first and second transistors, said source and drain regions forming act further comprising performing a DDD implant to from DDD source and DDD drain regions for the first transistor.
In another embodiment, the method further includes: performing a LDD implant to form LDD source and LDD drain regions for the second transistor; after both said DDD and LDD implants, forming main spacers adjacent the off-set spacers of the first and second transistors; and after forming said main spacers, performing a source/drain (S/D) implant to form a highly doped region within each of the DDD d
Chou Kai-Cheng
Rabkin Peter
Wang Hsingya Arthur
Hynix / Semiconductor Inc.
Mulpuri Savitri
Townsent and Townsend and Crew LLP
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