Transistor with ultra shallow tip and method of fabrication

Details Transistor with ultra shallow tip and method of fabrication Transistor with ultra shallow tip and method of fabrication

1994-12-23

1998-01-20

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 19, 257 65, 257336, 257377, 257382, 257385, 257408, 257742, 257755, 257773, 437 41, 437 43, 437 90, 437101, 437162, 437189, 437191, 437192, 437203, 437228, 437233, 437913, H01L 2906, H01L 21265

Patent

active

057104506

ABSTRACT:
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

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patent: 5285088 (1994-02-01), Sato et al.
patent: 5336903 (1994-08-01), Ozturk et al.
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patent: 5405795 (1995-04-01), Beyer et al.
Pfiester, J.R., et al., Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS, IEDM92, (1992) pp. 885-888., Jan.
Wong, S.S., et al., Elevated Source/Drain MOSFET, IEDM84, (1984) pp. 634-637., Jan.
Wu, Kevin et al., Fabrication and Characterization of the Hot-Carrier Suppressed (HCS) MOSFET, SRC TechCon '93, p. 539., Jan.
Yau, L.D., A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFETS, Solid State Electronics, (1971) pp. 1059-1062., Jan.

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