Transistor with shaped gate electrode and method therefor

Details Transistor with shaped gate electrode and method therefor Transistor with shaped gate electrode and method therefor

2000-06-02

2002-11-05

Fahmy, Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S735000, C438S738000

Reexamination Certificate

active

06475841

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to semiconductor devices, and more particularly to a transistor having a shaped gate electrode structure.
RELATED ART
In many prior art semiconductor transistors a generally uniform vertical gate profile was often desired. This is due to the fact that a generally uniform vertical gate would reduce parasitic electric effects associated with non-vertical gate profiles. Conventional etching techniques result in slight lateral etching at the top of the gate because the masking layer is gradually eroded during the etch. This results in a slight taper of the gate (narrow at the top, wide at the bottom near dielectric). This is undesirable, since the top is typically silicided, and narrowing here limits electrical conduction. Also, due to concerns with over etching of the underlying gate dielectric or substrate, etching processes had to be closely controlled to minimize such potentially damaging over etching conditions. As such, tapered regions or “feet” that extend horizontally from the generally vertical gate profile could result at the interface of the gate and the underlying gate oxide. These tapered regions are undesirable due to the additional parasitics that they introduce, where one such additional parasitic is an increase in the Miller capacitance of the transistor.
Although generally vertical gate profiles do reduce some parasitics, such profiles limit the potential for optimization of the device architecture in which they are included. Such optimizations can be based on different implantation steps, where some of these implementation steps may utilize angular implantation. Due to the generally vertical profile of the gate structure, closely spaced devices can limit the angle with which such angular implantation steps can be performed. In many cases, the offset between different implantation steps is important, and the limitation of the maximum angle with which specific angular implantation steps can be performed restricts the maximum offset that can be achieved between different implantation steps. This problem is compounded as device densities on integrated circuits continue to increase.
Therefore, gate structures that allow for more selective and controllable etching operations as well as increased effective angles of implantation are desired.


REFERENCES:
patent: 4026733 (1977-05-01), Owen, III et al.
patent: 4330931 (1982-05-01), Liu
patent: 4438556 (1984-03-01), Komatsu et al.
patent: 4634494 (1987-01-01), Taji et al.
patent: 4696877 (1987-09-01), Matsui et al.
patent: 4718973 (1988-01-01), Abraham et al.
patent: 5783478 (1998-07-01), Chau et al.
patent: 5834817 (1998-11-01), Satoh et al.
patent: 6124177 (2000-09-01), Lin et al.
T. Ghani et al., “100 nm Gate Length High Performance/Low Power CMOS Transistor Structure”, 1999 IEDM, pp. 17.1.1-17.1.4.
M. Zhang et al., “Reactive ion etching for submicron structures of refractory metal silicides and polycides”, pp. 1037-1041.
C. Monget et al., “Germanium etching in high density plasmas for 0.18 &mgr;m complementary metal-oxide-semiconductor gate patterning applications”, 1998 American Vacuum Society Technology B, vol. 16, No. 4, Jul./Aug. 1998, pp. 1833-1840.
S. Vallon et al., “Polysilicon-germanium gate patterning studies in a high density plasma helicon source”, 1997 American Vacuum Society Technology A 15(4), Jul./Aug. 1997, pp. 1874-1880.

Affiliated with

Also associated with

Rating

Transistor with shaped gate electrode and method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor with shaped gate electrode and method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor with shaped gate electrode and method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2955642