Transistor with reduced gate-to-source capacitance and...

Details Transistor with reduced gate-to-source capacitance and... Transistor with reduced gate-to-source capacitance and...

2006-04-11

2006-04-11

Quach, T. N. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C257S341000

Reexamination Certificate

active

07026204

ABSTRACT:
A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate this, the gate finger is strapped to a metal line at tabs adjacent to the finger gate over the active area, typically over the source, but the tabs add gate-to-source capacitance. This was previously quite small but as gate dielectrics have gotten thinner there is more capacitive coupling to the substrate by the tabs, and as gates have gotten thinner there is more resistance in the polysilicon finger gates. Both have the effect of increasing the RC time constant of the gate finger. This increase in RC time constant is alleviated by increasing the thickness of the dielectric separating the tabs from the substrate thereby reducing the capacitance caused by the tabs.

REFERENCES:
patent: 5025296 (1991-06-01), Fullerton
patent: 5434095 (1995-07-01), Hollinger
patent: 5592006 (1997-01-01), Merrill
patent: 5614751 (1997-03-01), Yilmaz et al.
patent: 5886938 (1999-03-01), Haukness
patent: 6023086 (2000-02-01), Reyes
patent: 6744117 (2004-06-01), Dragon et al.

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