Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-31
2001-03-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S347000, C257S386000
Reexamination Certificate
active
06198142
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor integrated circuits, and more specifically to a metal oxide semiconductor transistor with minimal junction capacitance and its method of fabrication.
DISCUSSION OF RELATED ART
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VLSI) circuits, such as microprocessors, memories, and applications specific integrated circuits (ICs). Presently, the most advanced ICs are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.5 &mgr;m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 &mgr;m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques and extend beneath gate electrode
102
. Formed adjacent to opposite sides of gate electrode
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As the gate length of transistor
100
is scaled down in order to fabricate a smaller transistor, the depth at which tip region
110
extends into substrate
106
must also be scaled down (i.e., decreased) in order to improve punchthrough characteristics of the fabricated transistor. Unfortunately, the length of tip region
110
, however, must be larger than 0.07 &mgr;m to insure that the later, heavy dose, deep source/drain implant does not swamp and overwhelm tip region
110
. Thus, in the fabrication of a small scale transistor with conventional methods, as shown in
FIG. 1
, the tip region
110
is both shallow and long. Because tip region
110
is both shallow and long, tip region
110
exhibits substantial parasitic resistance. Parasitic resistance adversely effects (reduces) the transistors drive current.
Another problem associated with MOS transistor
100
is that the junction capacitance (i.e., the capacitance of the p-n junction between the source/drain region
120
and substrate
100
) degrades device performance. In order to decrease junction capacitance, silicon-on-insulator (SOI) techniques have been proposed wherein devices are formed on a silicon layer deposited onto an insulator such as an oxide. Although good device performance can be achieved utilizing SOI technology, SOI substrates are difficult, if not impossible, to manufacture without excessive defects. The high cost and high defect density associated with SOI substrates make present SOI technology unmanufacturable. Another problem associated with SOI substrates is known as “floating body effect” which is due to the fact that the transistor substrate region is separated from the bulk substrate by an intermediate insulating layer. The “floating body effect” adversely affects circuit operation.
Another solution proposed to reduce junction capacitance of an MOS device is a localized SOI process such as described in U.S. Pat. No. 4,700,454 and assigned to the present assignee. In such a process, as shown in
FIG. 1
b
, oxygen atoms are implanted deep, at least 3500 Å, into the silicon substrate
150
in order to form buried oxide regions
152
. Source/drain regions
154
are subsequently implanted into the silicon substrate to form source/drain regions
154
above the buried oxide regions
152
. Implanting oxygen ions deep into a silicon substrate, however, requires a high energy implant, about 200 keV, which can cause substantial generation of defects and dislocations. Dislocations can create a high leakage current thereby making the fabricated device inoperable. Still further, by ion implanting oxygen atoms deep into the substrate, oxygen atoms have a gaussian distribution in substrate
150
resulting in a sprawling or unconfined buried oxide region
152
. A sprawling or unconfined buried oxide region causes a nonabrupt source/drain regions which can detrimentally affect device performance and can make scaling the device to small dimensions difficult. Additionally, since the source/drain regions are formed by ion implantation into the substrate region previously implanted with oxygen atoms, the source/drain regions are contaminated with oxygen atoms and silicon dioxide molecules (i.e, the source/drain regions contain at least 10×10
10
oxygen atoms/cm
3
).
Thus, what is desired is a transistor with an ultra shallow tip, which has reduced junction capacitance and which can be fabricated with a VLSI manufacturable process.
SUMMARY OF THE INVENTION
A novel MOS transistor with reduced junction capacitance and its method of fabrication is described. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A semiconductor material is deposited into the recesses to form a pair of source/drain regions.
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N. Hatzopoulos, et al.; “Buired Insulator Formation by Nitrogen Implantation at Elevated Temperatures”; 1991;Elsevier Science Publishers BV. (North-Holland) pp. 734-737.
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Chau Robert S.
Jan Chia-Hong
Packan Paul
Taylor Mitchell C.
Chaudhuri Olik
Chen George
Intel Corporation
Peralta Ginette
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