Partially non-volatile dynamic random access memory formed...

Details Partially non-volatile dynamic random access memory formed... Partially non-volatile dynamic random access memory formed...

1999-07-30

2001-07-24

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S222000

Reexamination Certificate

active

06266272

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to semiconductor memories and, more particularly, to a partially non-volatile DRAM which is formed by a plurality of single transistor cells used as DRAM cells and EPROM cells.
BACKGROUND OF THE INVENTION
CMOS technology has evolved such that the computer market has rapidly opened up to a wide range of consumers. Today's multi-media computer uses 64 MB main memory typically with 64 Mb Dynamic Random Access Memories (DRAMs). In the near future, 1 GB main memory will become commonplace, which will suggest a potentially strong research and development for 1 Gb DRAMs and beyond, with extremely deep sub-micron technology. Despite the main memory density requirement, it is even more important in the memory marketplace to have non-volatile memory features in a system. The typical NVRAMs (Non-Volatile Random Access Memory) are a mask-ROM, an EPROM (Electrically Programmable Read Only Memory), or a flash-RAM, and used for ID, BIOS, or core of the O/S (Operating System). These NVRAMs, however, have a unique and different standard from the DRAM standard used for a main memory configured with DRAMs. This results in copying the information stored in the NVRAM to the DRAM during the system initialization phase. A DRAM compatible flash-RAM allows for direct execution, which is an ideal solution. It is, however, inflexible to configure the density of the chip, since it had been pre-determined in the chip design. The unused bits are difficult to use for a general purpose main memory because of a poor write-speed and a limited endurance.
OBJECTS OF THE INVENTION
It is, therefore, an object of the invention to provide a Partially Non-Volatile Dynamic Random Access Memory (PNDRAM).
It is another object of the invention to structure the PNDRAM with one transistor cells (1T Cells), each preferably consisting of a DRAM cell and an EPROM cell.
It is still another object of the invention to have the PNDRAM to allow IDs, BIOS or the core of an operating System (O/S) to be stored in the EPROM cells.
It is yet another object of the invention to have the 1T cells that are not used for the EPROM cells to behave as conventional DRAM cells.
It is further object of the invention to have the control protocol to access the DRAM cells and the EPROM cells to be fully compatible with existing DRAM standards.
SUMMARY OF THE INVENTION
Herein described is a semiconductor memory referred to as Partially Non-Volatile Dynamic Random Access Memory (PNDRAM). The PNDRAM consists of a plurality of one transistor (1T) or two transistor (2T) cells, acting as DRAM cells and EPROM cells. The PNDRAM allows the BIOS or the core of the OS to be stored in EPROM cells in manufacturing or in a field. The 1T (or 2T) cells, which are not used for the EPROM cells, work as conventional DRAM cells for a main memory. The control protocol to access the DRAM cells and the EPROM cells can be fully compatible with existing DRAM standards, making the direct execution possible without requiring complicated logic. The addressing space for the DRAM cells and the EPROM cells can also be flexibly configurable.
In one aspect of the invention, there is provided a partially non-volatile DRAM array formed by a plurality of cells, wherein a first subset of the plurality of cells acts as DRAM cells and a second subset of the plurality of cells acts as EPROM cells.
In a second aspect of the invention, there is provided a partially non-volatile DRAM array formed by a plurality of DRAM cells, wherein a subset of the plurality of DRAM cells is programmed to behave as EPROM cells.
In a third aspect of the invention, there is provided a method of structuring a DRAM made of a plurality of cells in a partially non-volatile memory, the method including the steps of having a first subset of the plurality of cells act as DRAM cells; and having a second subset of the plurality of cells behaves as EPROM cells.


REFERENCES:
patent: 4611309 (1986-09-01), Chuang et al.
patent: 5126969 (1992-06-01), Kawana
patent: 5325327 (1994-06-01), Ema
patent: 5359571 (1994-10-01), Yu

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