Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-24
2004-01-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S300000, C438S303000
Reexamination Certificate
active
06677208
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuits, and more particularly to transistors with bottomwall and sidewall junction capacitance reduction regions and a method for forming the same.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are formed in and on a substrate and are interconnected to form an integrated circuit. One type of transistor is the metal oxide semiconductor field effect transistor (MOSFET) in which current flows through a narrow conductive channel between a source and drain and is modulated by an electric field applied at the gate electrode.
A problem with MOSFET transistors is bottomwall and sidewall capacitance which degrades device performance and can reduce the speed of a circuit. Efforts to bottomwall and sidewall junction capacitance have included tailoring of pocket implants, channel stop, and threshold adjust source/drain implants. All these implants serve other primary purposes. For example, pockets are used to minimize short channel effects. Threshold adjust is used for controlling device threshold. Channel stop is used for achieving isolation. Very deep source/drain implants result in increased short channel effects. For minimizing the bottomwall and sidewall junction capacitance, these implants require complex co-optimization and the reduction in bottomwall/sidewall capacitance may thus be limited.
SUMMARY OF THE INVENTION
The present invention provides a transistor with a bottomwall/sidewall junction capacitance reduction region that substantially eliminates or reduces the disadvantages and problems associated with prior systems and methods.
In accordance with one embodiment of the present invention, a method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.
Technical advantages of the present invention include that the bottomwall/sidewall junction capacitance reduction can be adjusted relatively independently of, and reduce the dependence of the bottomwall and sidewall junction capacitance on, other implants and aspects of transistor fabrication (pocket implants, channel stop, threshold adjust, deep source/drains).
Another technical advantage of the present invention is the achievement of the ultra-low bottomwall and sidewall capacitance reduction (<0.7 fF/um2) needed for high-performance logic design.
Yet another technical advantage is that the same masking configuration may be used during the implantation of the source and drain regions and the bottomwall/sidewall junction capacitance reduction region, and no additional masking or etching step is required for formation of the bottomwall/sidewall junction capacitance reduction region.
Certain embodiments may possess none, one, some, or all of these technical features and advantages and/or additional technical features and advantages.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
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patent: 6093610 (2000-07-01), Rodder
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patent: 6524901 (2003-02-01), Trivedi
Liu Kaiping
Mehrotra Manoj
Brady III W. James
Lindsay Jr. Walter L.
McLarty Peter K.
Niebling John F.
Telecky , Jr. Frederick J.
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