Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-01-08
2000-08-01
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438510, 438514, H01L 21336
Patent
active
060966106
ABSTRACT:
A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized. Furthermore, with the transistor layout described herein having at least a portion of the first diffusion region disposed within the well, adequate device isolation is also realized.
REFERENCES:
patent: 3600642 (1971-08-01), Allison et al.
patent: 3883372 (1975-05-01), Lin
patent: 4394674 (1983-07-01), Sakuma et al.
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 4730129 (1988-03-01), Kunitoki et al.
patent: 5112766 (1992-05-01), Fujii et al.
patent: 5252848 (1993-10-01), Adler et al.
patent: 5278787 (1994-01-01), Iwasa
patent: 5296409 (1994-03-01), Merrill et al.
patent: 5306656 (1994-04-01), Williams et al.
patent: 5334880 (1994-08-01), Abadeer et al
patent: 5369045 (1994-11-01), Ng et al.
patent: 5371394 (1994-12-01), Ma et al.
patent: 5374843 (1994-12-01), Williams et al.
patent: 5399917 (1995-03-01), Allen et al.
patent: 5414364 (1995-05-01), McCollum
patent: 5420450 (1995-05-01), Yoneda et al.
patent: 5434531 (1995-07-01), Allen et al.
patent: 5465054 (1995-11-01), Erhart
patent: 5514608 (1996-05-01), Williams et al.
patent: 5514980 (1996-05-01), Pilling et al.
patent: 5536666 (1996-07-01), Miller et al.
patent: 5574303 (1996-11-01), Terasima et al.
patent: 5578509 (1996-11-01), Fujita
patent: 5583454 (1996-12-01), Hawkins et al.
patent: 5661048 (1997-08-01), Davies et al.
patent: 5776811 (1998-07-01), Wang et al.
Wolf, S.; Silicon Processing for the VLSI Era vol. 3: The Submicron MOSFET, Sunset Beach, CA, pp.636 637, Jan. 1995.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, p. 124, Jan. 1986.
"Metal-to Metal Antifuses with Very Thin Silicon Dioxide Films", Zhang et al., pp. 310-312, IEEE, 1994.
CMOS Technology and Devices, Masakazu, S., pp. 74-75, AT&T, 1988.
VSLI Technology, 2nd Edition, Sze, S.M., pp. 466-513, AT&T, 1988.
Alavi Mohsen
Ghani Tahir
Intel Corporation
Lattin Christopher
Niebling John F.
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