Transistor structures and processes for forming same

Details Transistor structures and processes for forming same Transistor structures and processes for forming same

2003-06-17

2004-10-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06808994

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor device and fabrication thereof and, more particularly, to Source-Drain On Insulator (SDOI) transistor structures and fabrication methods thereof.
BACKGROUND OF THE INVENTION
Semiconductor devices utilize Source-Drain On Insulator (SDOI) transistors for various applications. An SDOI transistor is a high performance transistor that has a very low junction capacitance, comparable to that of a Silicon On Insulator (SOI) transistor, but doesn't possess a floating body effect that is prevalent in SOI transistors.
The floating body effect of an SOI transistor has some advantages and some disadvantages. On the positive side, it results in higher current drive and better substrate-threshold voltage (V
T
) swing (body effect is defined as V
T
sensitivity to body voltage drop (Vb)). On the negative side it can result in history effect and high off-state current leakage. It is advantageous to use SOI transistors on circuits that need high current drive and are tolerant to off-state current leakage. However, for other circuits, such as pass gate logic, the floating body effect will cause problems.
One example of the undesirable operations the floating body effect may cause in a pass logic gate may be seen in an example wherein: Vc equals the control voltage, Vt equals the transistor threshold voltage, and Vb equals the body voltage. During the “on” state the gate is at Vc, the source is at Vc, the drain is at Vc−V
T
, and the body is at approximately Vc−V
T
. When the device is switched to the “off” state, the gate goes to zero volts, the source stays at Vc and the body goes to Vb~Vc/2 (i.e., the history effect). When the drain switches to zero volts, the n+ junction between the source and the body becomes forward biased and will draw large bipolar current (i.e., undesirable high current drive).
The present invention addresses various characteristics of devices, such as an SOI transistor, and particularly addresses such issues as history effect and high current drive. A significant focus of the present invention comprises SDOI field effect transistor structures and fabrication methods thereof, which will become apparent to those skilled in the art from the following disclosure.
SUMMARY OF THE INVENTION
An exemplary implementation of the present invention includes source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried depletion layer under the channel region, which provides electrical isolation between the body and the channel of each transistor structure.
Another exemplary implementation of the present invention include source-drain on insulator (SDOI) transistor structures (n-channel and p-channel transistor structures) comprising a buried p-n junction under the channel region, which provides substantial (if not complete) electrical isolation between the body and the channel of each transistor structure.
In one exemplary implementation, an SDOI transistor structure is formed by creating electrical isolation below the SDOI transistor channel region that spans completely between the SDOI insulators. The electrical isolation may be formed by implanting an appropriate conductive dopant to form a depletion layer below the channel region.
In an alternate exemplary implementation, the electrical isolation may be formed by implanting an appropriate conductive dopant to form a p-n junction below the channel region of an SDOI transistor structure that spans completely between SDOI insulators.


REFERENCES:
patent: 6174754 (2001-01-01), Lee et al.
patent: 6548383 (2003-04-01), Trivedi et al.
“Pseudo-SOI: P-N-P Channel-Doped Bulk MOSFET for Low-Voltage High-Speed Applications”, M. Miyamoto et al., IEE Transactions on Electron Devices, vol. 48, No. 12. Dec. 2001. Pp. 2856-2860.

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