Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-21
2003-07-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C257S288000
Reexamination Certificate
active
06589831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor device structures and manufacturing methods thereof, and more particularly, this invention relates to semiconductor devices having non-planar channel structures which increase the channel lengths thereof, and to methods of manufacturing such devices.
2. Description of Related Art
Semiconductor devices such as field effect transistors (FETs) are becoming increasingly important in low power applications. As FET devices are scaled to smaller and smaller dimensions, manufacturers must refine transistor designs to maintain optimum device performance.
A conventional transistor structure and manufacturing method thereof will be described below with reference to FIG.
1
.
Referring to
FIG. 1
, a device isolation layer is formed on a predetermined region of a silicon substrate
10
, and then a gate oxide layer
12
and a gate electrode
16
are formed on the silicon substrate
10
. Next, an oxide or a nitride spacer
18
is formed on the sides of the gate electrode
16
, and then, ion implantation is performed such that source/drain regions
20
having a lightly doped drain (LDD) configuration are formed.
As the integration of semiconductor devices increases, it becomes necessary to reduce the size of the transistors of such devices. For example, in conventional memory cell designs that use planar transistors, such as the device shown in
FIG. 1
, the cell size is minimized by scaling lithographic features F, where F is the minimum line width of the feature size that can be patterned with lithography. Accordingly, if a minimum cell size is to be obtained, it is necessary to reduce the size of the transistor as much as possible. This, in turn, reduces the channel length of the device.
However, when the channel length is decreased, performance degradations occur in the device. Electrical characteristics of the device, such as hot-carrier injection, drain leakage current, and punch through become poor. For a memory cell including such a device, data retention time decreases and power consumption increases due to the resultant short channel effects.
SUMMARY OF THE INVENTION
The present invention is at least partially characterized by a transistor having a non-planar channel structure in which epitaxial layers are used to form elevated source and drain regions over a silicon subtrate, and by a method of manufacturing such a transistor.
According to one aspect of the present invention, a semiconductor device includes a semiconductor substrate having a surface, and first and second epitaxial layers spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the-substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate.
According to another aspect of the present invention, a method of manufacturing a semiconductor device includes selectively growing first and second epitaxial layers over a surface of a semiconductor substrate, forming a gate insulating layer over at least a portion of the first and second epitaxial layers and the surface of the semiconductor substrate, forming a gate electrode over the gate insulating layer such that the gate electrode extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap, and forming first and second impurity regions within the first and second epitaxial layers, respectively.
According to the invention, a non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.
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patent: 5945707 (1999-08-01), Bronner et al.
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patent: 6403434 (2002-06-01), Yu
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Kamata et al. (U.S. patent Application Publication US 2002/0063299 A1).
Nelms David
Nguyen Thinh T.
Volentine & Francos, PLLC
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