Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1993-11-30
2004-08-24
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S763000
Reexamination Certificate
active
06780718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices and more specifically to field effect devices such as field effect transistors (FET) for use in integrated circuits.
2. Description of the Prior Art
In manufacturing transistors, re-oxidation has been used in 5 &mgr;m to 1.2 &mgr;m technologies to improve transistor lifetimes and gate oxide reliability due to higher fields occurring at the etched polysilicon transistor edges. For example, U.S. Pat. No. 4,553,314 teaches using re-oxidation to manufacture semiconductor devices. Typically, 3 &mgr;m and 5 &mgr;m technologies use re-oxidation thicknesses from about 1200 Å to about 2500 Å depending on the particular device. In 1.5 &mgr;m and 2 &mgr;m technologies, re-oxidation thicknesses from about 500 Å to about 1,000 Å are used.
In 0.8 &mgr;m technology, however, the re-oxidation process has been discontinued because the lifetimes of transistors currently manufactured without the re-oxidation process is better than with the re-oxidation process. Such a situation is caused by the formation of asperities on the underside of the polysilicon layer of the transistor during the re-oxidation process. These asperities are of little importance until the gate oxide thicknesses are reduced to below 200 Å as used in submicron technology. At this point, the asperities become a contributor to the increased field at the transistor edge and of hot carrier injection (HCI). These asperities are caused by (1) oxidant diffusion along polysilicon grain boundaries creating single crystal silicon protrusions and (2) oxide thicknesses under the polysilicon edge increasing during re-oxidation, causing polysilicon grain boundary slip to occur and creating multiple edges, which results in an overall increase in angle geometries.
In addition, moving to device geometries below 0.8 &mgr;m technology has resulted in marginal lifetimes of the transistors. Thus, it is desirable to have a gate structure that has an increased lifetime using re-oxidation under the gate edge but without the asperities caused by presently used re-oxidation processes.
SUMMARY OF THE INVENTION
The present invention is a gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure. The nitride layer prevents the formation of asperities on the underside of the polysilicon layer during reoxidation of the transistor.
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Booth Richard A.
Jorgenson Lisa K.
Munck William A.
STMicroelectronics Inc.
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