Transistor storage

Details Transistor storage Transistor storage

1982-06-10

1984-12-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

044882645

ABSTRACT:
A transistor storage for entering and storing information in and simultaneously reading information from two columns of a matrix of memory cells with different addresses. The transistor storage comprises two multidigit data buses connected to the columns of the memory cell matrix. Each memory cell of the matrix comprises a storage element and two induced channel transistors connected to the storage element and to the multidigit data buses. The multidigit data buses are connected to write circuits and read amplifiers of a first readout direction and second readout direction, which are connected to an input multidigit data bus and an output multidigit data bus. The write circuits are connected to write and read buses. The read amplifiers are connected to the read bus. A multidigit address bus of the transistor storage is connected to address decoders of the first and second matrix columns; these are connected to access control circuits connected to the write and read buses and to the transistors of all the memory cells of a respective matrix column.

REFERENCES:
patent: 4445203 (1984-04-01), Iwahashi
cf. Electronica, 1974, vol. 47, No. 5, pp. 37-41.

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