Transistor sidewall spacers composed of silicon nitride CVD...

Details Transistor sidewall spacers composed of silicon nitride CVD... Transistor sidewall spacers composed of silicon nitride CVD...

1998-03-25

2001-01-09

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S791000, C438S792000

Reexamination Certificate

active

06171917

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming transistor sidewall spacers from silicon nitride which has been deposited from a high density plasma source, thereby enhancing the properties of the integrated circuit employing the transistor.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Operating transistors which have heavily doped source/drain regions arranged directly adjacent the gate conductor often experience a problem known as hot carrier injection (“HCI”). HCI is a phenomena by which the kinetic energy of the charged carriers (holes or electrons) is increased as they are accelerated through large potential gradients, causing the charged carriers to become injected into and trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field (“Em”) occurs near the drain during saturated operation. As a result of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in a NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems of sub-threshold current and threshold shift resulting from HCI, an alternative drain structure known as the lightly doped drain (“LDD”) is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section within the active area (hereinafter “junction”) at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. The second implant dose forms a heavily doped source/drain region within the junction laterally outside the LDD area. A dopant gradient (“graded junction”) results in which the dopant concentration within the junction decreases in a lateral direction toward the channel.
Formation of sidewall spacers adjacent to the gate conductor typically involves chemical vapor deposition (“CVD”) of silicon dioxide (“oxide”) from a low density plasma source created within a reaction chamber. The plasma is generated by applying a radio-frequency (“RF”) electric field to a low pressure gas containing reactant molecules, e.g., silane and oxygen-containing species. The RF field causes electrons to be stripped from their respective atoms and gain kinetic energy. The high-energy electrons collide with gas molecules, thereby causing dissociation and ionization of the, reactant molecules. The energetic species, primarily radicals, that form are then adsorbed on the surface of the semiconductor topography which is positioned within the reaction chamber. While upon the topological surface, they diffuse to stable sites where they react with other adsorbed species to form oxide as well as other molecules.
The RF power is applied at a relatively low frequency of approximately 450 KHZ to 13.5 MHz. Consequently, the degree of ionization is extremely low, and a low density plasma (10
8
to 10
10
ions/cm
3
) is generated which contains only a fraction of excited neutral atoms. It is postulated that the number of oxygen radicals produced may not be sufficient to combine with all of the silicon radicals produced. The highly reactive silicon radicals that become adsorbed on the semiconductor topography thus may combine with atoms other than oxygen. The resulting deposited oxide is non-stoichiometric and may contain by-products such as hydrogen which are bonded to the silicon. The relatively weak Si—H bonds can be easily broken in subsequent annealing steps, allowing hydrogen atoms within the oxide spacers to migrate into the gate conductor, the gate oxide, the junctions, and/or the channel of the transistor. Hydrogen atoms positioned within these areas of the transistor can cause, for example, the threshold voltage of the transistor to shift undesirably from its design specification.
Using an RF field to create the plasma can also lead to surface damage of the semiconductor topography. The motion of the excited species within the plasma is not strictly controlled. The ions of the plasma can bombard the semiconductor topography at a force sufficient to damage portions of the substrate and the gate conductor. Moreover, the highly reactive radicals that form can collide with gas molecules and undergo a homogeneous gas-phase nucleation to form relatively course particulates which can contaminate the deposited oxide. Such contaminates can lead to outgassing, cracking, or peeling when subjected to changing temperature conditions during later processing steps. The contaminates can also cause threshold shifts in the transistor-containing oxide spacers formed from the CVD deposited oxide.
Integrated circuit formation involves electrical linkage of various active devices, i.e., transistors. Contacts are formed through an interlevel dielectric down to the electrically active areas, and multiple levels of dielectrically isolated interconnect are routed to the contacts. With the desire to build faster, more complex integrated circuits, the use of local interconnect which extend over relatively short routing distances has become increasingly popular. Local interconnect can be used to provide coupling between a gate of a MOS transistor and, e.g., a source or drain junction of that transistor or of another transistor. Formation of a contact coupled to the gate conductor involves etching an opening vertically through an oxide interlevel dielectric down to the gate conductor using a conventional optical lithography technique and an etch technique highly selective to the oxide interlevel dielectric. Unfortunately, misalignment of the photoresist masking layer may occur during optical lithography, permitting ion bombardment of the oxide sidewall spacers during the etch step. Substantial misalignment and/or bombardment of the spacers will remove them from between the gate conductor and the source/drain junction. Thus, when a conductive material, such as tungsten is deposited into the contact opening, it may become arranged laterally adjacent to the gate conductor in regions where the sidewall spacers have been removed. This configuration of the conductive material may provide for unwanted capacitive coupling or electrical linkage between the gate conductor and the source/drain regions.
It is therefore desirable to devise a method for forming sidewall spacers comprising a high quality dielectric laterally adjacent to the gate conductor of a transistor. In other words, the dielectric from which the spacers are formed should be stoichiometric. It is necessary that the sidewall spacers contain no contaminates which could be detrimental to the operation of the transistor. The sidewall spacers must effectivel

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