Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2008-07-01
2008-07-01
Dickey, Thomas L (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S734000, C257SE21429
Reexamination Certificate
active
07393769
ABSTRACT:
According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.
REFERENCES:
patent: 6031261 (2000-02-01), Kang
patent: 6423618 (2002-07-01), Lin et al.
patent: 09-045904 (1997-02-01), None
patent: 2002-0032934 (2002-05-01), None
patent: 2002-0044861 (2002-06-01), None
English language abstract of Japanese Publication No. 09-045904.
English language abstract of Korean Publication No. 2002-0032934.
English language abstract of Korean Publication No. 2002-0044861.
Kim Ki-nam
Seo Hyeoung-won
Song Du-Heon
Yang Woun-Suck
Dickey Thomas L
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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