Transistor mobility improvement by adjusting stress in...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S385000, C257S377000, C438S439000

Reexamination Certificate

active

11004690

ABSTRACT:
A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.

REFERENCES:
patent: 6133105 (2000-10-01), Chen et al.
patent: 6339018 (2002-01-01), Ballantine et al.
patent: 6429061 (2002-08-01), Rim
Ge, C.-H., et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEEE, Mar. 2003, 4 pages.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” IEEE, 2001, 4 pages.
Lee, J.-H., et al., “A Study of Stress-Induced p+
Salicided Junction Leakage Failure and Optimized Process Conditions for Sub-0.15- μm CMOS Technology,” IEEE Transactions on Electron Devices, vol. 49, No. 11, Nov. 2002, pp. 1985-1992.

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