Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-05
2003-12-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S978000, C257S408000
Reexamination Certificate
active
06656808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same, and more particularly, to a transistor having an enlarged gate area at an upper portion thereof to achieve a stabilized electrode size, and an advantageous method of manufacturing the same.
2. Description of the Related Art
The elements of a semiconductor device are becoming more densely integrated to improve the processing speed and increase the memory capacity. Manufacturing processes for 16 M and 64 M dynamic random access memory (DRAM) devices are being replaced by 256 M manufacturing processes, and mass production techniques for 1 G devices are rapidly evolving. However, with increases in processing speed and memory capacity, the manufacturing techniques to produce the devices must take into account certain manufacturing limitations in the pursuit of delivering increasingly complex and integrated devices.
A semiconductor device is generally manufactured by forming a multi-layer structure, including dielectric layers and conductive layers, and with minute patterns having a design rule of 0.15 &mgr;m or less. One of the most important goals in semiconductor design is to increase the speed of the device, which typically means reducing the size of a gate of a transistor. However, manufacturing a device having a feature size of 100 nm or less by utilizing present photolithography patterning techniques is very difficult. Accordingly, a method utilizing an SiON hard mask has been utilized to reduce the size of the gate.
FIGS. 1A-1H
are schematic cross-sectional views explaining a method of manufacturing a transistor according to the conventional SiON method.
Referring to
FIG. 1A
, a gate oxide layer
110
having a thickness of about 100-150 Å is formed on a semiconductor substrate
100
. On the gate oxide layer
110
, polysilicon is deposited to a thickness of about 2500 Å to form a polysilicon layer
120
, and then SiON is deposited on the polysilicon layer to a thickness of about 800 Å to form an anti-reflective layer
130
. The anti-reflective layer
130
is applied in those cases where the reflectivity of an underlying layer is high, when the step coverage of the underlying layer is great, or when the critical dimension of a pattern is very small. On the anti-reflective layer
130
, a photoresist is coated and then is patterned by a photolithography to form a photoresist pattern
142
.
Referring to
FIG. 1B
, a SiON pattern
132
is formed by patterning and etching a second photoresist pattern
144
, which has a reduced size when compared with the photoresist pattern
142
. A dry etching process utilizing O
2
may be used to form the SiON pattern
132
. Generally, the photoresist is mainly composed of carbon and hydrogen, and so, the photoresist pattern is advantageously etched by oxygen, while forming CO
2
, CO, H
2
O, and the like.
Referring to
FIG. 1C
, the photoresist pattern
144
is removed by a strip method to form a hard mask using the SiON pattern
132
(hereinafter, referred to as SiON hard mask). The hard mask functions as an etching mask even though it is not the photoresist pattern. However, the hard mask has a higher etching selectivity than that of the photoresist pattern.
Referring to
FIG. 1D
, the underlying polysilicon layer
120
is etched to form a polysilicon pattern
122
by utilizing the SiON hard mask
132
. In order to etch the polysilicon, a mixture of carbon tetrachloride and argon gas, a mixture of carbon tetrafluoride and oxygen gas, CF
3
Cl gas, a mixture of carbon fluoride-based compound and chlorine gas, etc. can be utilized.
Referring to
FIG. 1E
, the SiON hard mask
132
is removed and then an impurity doping process is performed utilizing the recently formed gate electrode
122
as a mask. A LDD (lightly doped drain)
102
a
is formed by doping an impurity having a low concentration.
Referring to
FIG. 1F
, a SiN layer is deposited and then an etch back process is implemented to form a spacer
150
on the side walls of the oxide pattern
122
. A HDD (heavily doped drain)
102
b
is formed by doping an impurity having a high concentration and using the SiN spacer
150
as a mask.
Referring to
FIG. 1G
, a cobalt layer
160
is formed by depositing cobalt (Co) on the whole surface of the gate electrode on which the spacer
150
is formed.
Referring to
FIG. 1H
, a heat treatment process is performed under a temperature range of about 700-900° C. so that the deposited cobalt reacts with the Si atoms on the underlying layer to form a CoSix compound. That is, a silicidation process is completed by respectively forming CoSix layers
124
and
114
on the oxide pattern and the substrate, except for the region where the SiN spacer
150
is formed.
By implementing a salicidation (i.e., a self-aligned silicide) process, a silicide compound can be selectively formed on a desired region. When metal compounds such as Ti, Ni, Co, etc. are deposited on a layer containing a silicon atom, and a heat treatment process is then performed, a silicide compound such as Ti-silicide, Ni-silicide or Co-silicide is formed by the interaction. After forming a dielectric layer on the silicide layer and then forming a contact hole by pattering the dielectric layer, this silicide layer can be advantageously exposed (self-aligned property). When a metallic layer is formed on the dielectric layer, the metallic layer advantageously makes contact with the silicon containing lower layer through the contact hole. Accordingly, this salicidation process is applied when manufacturing a device having a minute critical dimension.
According to the above-described method, a gate electrode having a critical dimension of about 0.10 &mgr;m can be obtained. However, certain problems result when the photoresist layer is etched by using O
2
as shown in
FIG. 1B
, since homogeneous etching is difficult because of the small pattern size.
In addition, when manufacturing a transistor with a gate electrode having a size of 0.13 &mgr;m or less, a spacer is generally formed on a side wall of the gate electrode and then the silicidation process is implemented to lower the resistance of the gate electrode. At this time, the polysilicon which forms the gate electrode has a compressive stress, and the SiN compound which forms the spacer has a tensile stress, which act counter to each other. Accordingly, the metal silicide compound formed on the gate electrode receives the tensile stress of the SiN spacers formed on the side walls of the gate electrode, which stresses are confronting each other from opposite spacer directions.
U.S. Pat. No. 5,734,185 discloses a method of manufacturing a stabilized and minute gate electrode and a transistor having a gate electrode where a longitudinal length at the upper portion is longer than that at the lower portion which contacts an underlying channel region. By employing this patented method, the number of the photolithography processes for manufacturing the transistor is reduced and so the number of the masks is reduced. In addition, the capacitance of the source-drain is reduced to improve the operating efficiency of the circuit. However, it is understood that the process for the manufacture of the transistor is complicated and the formation of the channel is not advantageous.
SUMMARY OF THE INVENTION
In view of the shortcomings in the conventional art described above, it is an object of the present invention to provide a stable and minute transistor having a gate electrode in which an upper horizontal width is greater than a lower horizontal width.
Another object of the present invention is to provide a method of manufacturing a transistor in which the production costs and processing time are reduced by utilizing just one photolithography process, and thereby reducing the number of the required masks.
To accomplish the first object, the present invention provides a transistor including a substrate and a gate electrode formed on the substrate. The gate electrode has an upper portion and a lower porti
Fourson George
Garcia Joannie Adelle
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