Transistor having ultrashallow source and drain junctions with r

Details Transistor having ultrashallow source and drain junctions with r Transistor having ultrashallow source and drain junctions with r

1998-08-19

1999-11-02

Arroyo, Teresa M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438229, 438232, 438277, 438302, 438306, 438209, 438525, H01L 218234

Patent

active

059769378

ABSTRACT:
Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126). The dopants are implanted in the first direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (166 and 168) of the second active area (142). Dopants may be implanted from a second direction substantially parallel to the second gate electrode (140) and perpendicular to the first direction into the source and drain sections (166 and 168) of the second active area (142). The dopants are implanted in the second direction at an angle at which the masking layer (160) blocks entry of the dopants into the source and drain sections (162 and 164) of the first active area (126).

REFERENCES:
1992 IEEE, IEDM 92-699, "High Carrier Velocity and Reliability of Quarter-Micron SPI (Self-Aligned Pocket Implantation) MOSFETs," pp. 28.3.1-28.3.4 (Atsushi Hori, Akira Hiroki, Mizuki Segawa, Takashi Hori, Akihira Shinohara, Mitsuo Yasuhira and Shigenobu Akiyama).
1993 IEEE, IEDM 93-119, "Sub-50 NM Gate Length N-MOSFETs With 10 NM Phosphorus Souce and Drain Junctions," pp. 6.2.1-6.2.4 (Mizuki Ono, Masanobu Saito, Takashi Yoshitomi, Claudio Fiegna, Tatsuya Ohguro and Hiroshi Iwai).

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