Transistor formed from stacked disposable sidewall spacer

Details Transistor formed from stacked disposable sidewall spacer Transistor formed from stacked disposable sidewall spacer

2003-03-31

2004-03-16

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S307000, C438S595000

Reexamination Certificate

active

06706605

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuits and are more particularly directed to an electronic circuit transistor (or transistors) formed from a stacked disposable sidewall spacer.
Semiconductor devices are prevalent in all aspects of electronic circuits, and an often critical and dominant element used in such circuits is the transistor. Thus, due to the evolution of electronic design and its criteria, considerable effort has been made to improve transistor design, including accommodating the ongoing effort to reduce device dimensions. During this history, both a conventional sidewall spacer process and a disposable sidewall spacer process have been developed, where in each case and as known in the art the sidewall spacers are used to align the source/drain implant regions of the transistor relative to the transistor gate. However, the conventional and disposable sidewall spacer processes have various attributes that can be improved upon, which is explored later after an introduction to these two known technologies.
In the known art of conventional transistor sidewall spacers and as further detailed later, after the transistor gate is formed, so-called lightly doped source/drain (“LDD”) regions are implanted into the underlying semiconductor region and self-aligned relative to both sides of the gate, where the average dopant concentration of the dopant profile in these regions is less than that of the deep source/drain regions that are implanted into the underlying semiconductor region at a lateral distance from the gate that is greater than that of the location of the LDD regions. More recently, the dopant concentration in these LDD regions has been increased and, hence, such regions are now more commonly referred to as medium doped source/drain (“MDD”) regions. Thus, for sake of consistency in the remainder of this document, the more contemporary example of MDD regions will be used. After the MDD regions are implanted, the device is annealed to thereby cause lateral extension of the MDD regions into the area below the gate. Thereafter, sidewall spacers are formed on the two gate sidewalls and the deep source/drain regions are implanted into the underlying semiconductor region, with the deep source/drain region implant self-aligning to the sidewall spacers. Thereafter, the deep source/drain regions are annealed. Note, therefore, because the MDD regions were previously formed, then the anneal directed to the deep source/drain regions necessarily exposes the previously-formed MDD regions to a second anneal (having been annealed once earlier after the implant of the MDD regions). The transistor art has recognized that the effect of this second anneal on the MDD regions may degrade the source/drain junction of the transistor and otherwise undesirably affect the transistor performance.
In the known art of transistor disposable sidewall spacers, two different flows are known, namely, a composite disposable sidewall spacer flow and an all nitride disposable sidewall spacer flow. Each of these processes is further described later, but at this point certain preliminary aspects are noted. Specifically, with respect to the disposable sidewall spacer flows, the second anneal exposure of the transistor MDD regions as described above with respect to the conventional process is avoided. Particularly, in the disposable sidewall spacer art, first a disposable sidewall spacer is formed on the outsides of the two gate sidewalls and the deep source/drain regions are then implanted, self-aligned to the respective disposable sidewall spacers, followed by an anneal of the deep source/drain regions. Thereafter, the disposable sidewall spacers are removed, hence giving rise to the name “disposable.” Next, the MDD regions are implanted and then annealed. Note, therefore, that the MDD regions are formed after the deep source/drain regions and, thus, the MDD regions do not incur the anneal of the earlier-formed deep source/drain regions; consequently, there is one less exposure of the MDD regions to an anneal as compared to the conventional process. This provides a more abrupt MDD profile, which is beneficial in reducing the transistor leakage. Further, the source/drain anneal can be tuned without concern of the MDD regions, whereas in the conventional process, since the source/drain anneal is known to also affect the MDD regions, then its parameters are typically adjusted with some consideration also to the effect that anneal will have on the MDD regions. As another benefit of the disposable sidewall spacer approach, a higher temperature source/drain region anneal may be performed, creating reduced dopant depletion in the gate. As known in the art, this improves (i.e., lowers) T
OX,INV
, where that reflects the desired goal of having sufficient dopants in the gate so as to reduce or avoid a capacitance that otherwise would add to the capacitance of the gate oxide, thereby degrading device performance. As still another benefit of the disposable sidewall spacer approach, the two anneals incurred by the deep source/drain regions grade the source/drain region junctions more than the conventional process, providing better diode characteristics. Still other benefits are known in the art.
While the preceding approaches to transistor formation have yielded many satisfactory integrated circuits, the present inventors have observed that these approaches also may be improved. Thus, in view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a method of forming an integrated circuit transistor, comprising providing a semiconductor region and forming a gate structure in a fixed position relative to the semiconductor region. The gate structure has a first sidewall and a second sidewall. The method also comprises first, forming a first layer adjacent the first sidewall and the second sidewall, and second, forming a second layer adjacent the first layer. The method also comprises third, forming a third layer adjacent the second layer, and fourth, forming a fourth layer adjacent the third layer. The method also comprises fifth, implanting a first and second source/drain region in the semiconductor region and at a first distance laterally with respect to the gate structure, wherein a combined thickness of the first, second, third, and fourth layers determines the first distance. The method also comprises sixth, removing the third and fourth layers, and seventh, implanting a third and fourth source/drain region in the semiconductor region and at a second distance laterally with respect to the gate structure, wherein the second distance is less than the first distance.
Other aspects are also disclosed and claimed.


REFERENCES:
patent: 4843023 (1989-06-01), Chiu et al.
patent: 5171700 (1992-12-01), Zamanian
patent: 5793089 (1998-08-01), Fulford et al.
patent: 6261913 (2001-07-01), Akram et al.
patent: 6316302 (2001-11-01), Cheek et al.

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