Transistor formation with local interconnect overetch immunity

Details Transistor formation with local interconnect overetch immunity Transistor formation with local interconnect overetch immunity

1998-08-14

1999-05-18

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, 438433, H01L21/336;21/76

Patent

active

059045345

ABSTRACT:
An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

REFERENCES:
patent: 4753901 (1988-06-01), Ellsworth et al.
patent: 5401678 (1995-03-01), Jeong et al.
patent: 5559368 (1996-09-01), Hu et al.
patent: 5734192 (1998-03-01), Sengle et al.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 1--Process Technology; pp. 210-226, 555-565; 1986.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 2--Process Integration; pp. 162-169, 318, 332-333, 354-361, 419-439; 1990.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 3--The Submicron MOSFET; pp. 367-407, 591-660; 1995.

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