Transistor formation for multilevel transistors

Details Transistor formation for multilevel transistors Transistor formation for multilevel transistors

1996-09-30

1999-09-07

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438152, 438166, 438217, 438231, 438270, 438301, H01L 218238

Patent

active

059500824

ABSTRACT:
A dual level transistor and a fabrication technique for making the transistor. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. A first local substrate is formed on an upper surface of the first inter-substrate dielectric. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.

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Vol. 2 S. Wolf, Silicon Processing for the VLSI Era, Lattice Press 1990, pp. 341-345.

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