Transistor fabrication methods using dual sidewall spacers

Details Transistor fabrication methods using dual sidewall spacers Transistor fabrication methods using dual sidewall spacers

2007-05-15

2007-05-15

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S184000

Reexamination Certificate

active

10899360

ABSTRACT:
Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

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