Transistor fabrication method

Details Transistor fabrication method Transistor fabrication method

1997-02-05

1999-02-09

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438269, 438303, H01L 21336

Patent

active

058693750

ABSTRACT:
A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.

REFERENCES:
patent: 5093275 (1992-03-01), Tasch, Jr. et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5270257 (1993-12-01), Shin
patent: 5371026 (1994-12-01), Hayden et al.
patent: 5430313 (1995-07-01), Kumagai et al.
Shin'ichiro Kimura et al., "Short-Channel-Effect-Suppressed Sub-0.1-.mu.m Grooved-Gate MOSFET's with W Gate", IEEE Transactions on Electron Devices, 42(1):94-99 (1995).

Affiliated with

Also associated with

Rating

Transistor fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor fabrication method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1948137