Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-08-09
2011-08-09
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S212000, C438S268000, C257SE21621, C257SE21625, C257SE21629, C257SE21633, C257SE21635
Reexamination Certificate
active
07994008
ABSTRACT:
A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
REFERENCES:
patent: 7101762 (2006-09-01), Cohen et al.
patent: 7141837 (2006-11-01), Coronel et al.
patent: 7381601 (2008-06-01), Kim et al.
patent: 2004/0016968 (2004-01-01), Coronel et al.
patent: 2004/0119142 (2004-06-01), Grossi et al.
patent: 2005/0167750 (2005-08-01), Yang et al.
patent: 2005/0184325 (2005-08-01), Jacquet et al.
patent: 2005/0189583 (2005-09-01), Kim et al.
patent: 2005/0239238 (2005-10-01), Schuele et al.
patent: 2005/0242398 (2005-11-01), Chen et al.
patent: 2006/0022275 (2006-02-01), Ilicali et al.
patent: 2006/0027881 (2006-02-01), Ilicali et al.
patent: 2006/0134882 (2006-06-01), Zhang
patent: 2006/0240622 (2006-10-01), Lee et al.
patent: 2009/0289304 (2009-11-01), Pouydebasque et al.
patent: 1020050033200 (2005-04-01), None
Wong, et al., “Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 mm Thick Silicon Channel,”Technical Digest, International Electron Devices Meeting (IDEM 97), Dec. 7, 1997, pp. 427-430; XP002391499.
Guarini, et al., “Triple-Self-Aigned, Planar Dougl-Gate MOSFETs: Devices and Circuits,”IDEM 2001; 19.2.1-19.2.4, pp. 425-428.
Preliminary French Search Report, FR 06 00970, dated Jul. 21, 2006.
Cerutti Robin
Coronel Philippe
Lenoble Damien
Skotnicki Thomas
Wacquez Romain
Gardere Wynne & Sewell LLP
Kim Su C
Smith Matthew
STMicroelectronics (Crolles 2) SAS
Szuwalski Andre M.
LandOfFree
Transistor device with two planar gates and fabrication process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor device with two planar gates and fabrication process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor device with two planar gates and fabrication process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2759017