Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-08-31
2000-05-16
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438529, H01L 21336
Patent
active
060636734
ABSTRACT:
In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, the invention includes a resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.
REFERENCES:
patent: 4837179 (1989-06-01), Foster et al.
patent: 4943537 (1990-07-01), Harrington, III
patent: 5122474 (1992-06-01), Harrington, III
patent: 5170232 (1992-12-01), Narita
patent: 5364807 (1994-11-01), Hwang
patent: 5389557 (1995-02-01), Jung-Suk
patent: 5416351 (1995-05-01), Ito et al.
patent: 5464785 (1995-11-01), Hong
patent: 5504024 (1996-04-01), Hsu
patent: 5565700 (1996-10-01), Chou et al.
patent: 5595919 (1997-01-01), Pan
patent: 5606191 (1997-02-01), Wang
patent: 5614752 (1997-03-01), Takenaka
patent: 5635743 (1997-06-01), Takahashi
patent: 5654574 (1997-08-01), Williams et al.
patent: 5731611 (1998-03-01), Hshieh et al.
patent: 5780895 (1998-07-01), Barret et al.
patent: 5891774 (1999-04-01), Ueda et al.
patent: 5923987 (1999-07-01), Burr
Buti, et al., "A New Asymmetrical source Gold Drain (HS-GOLD) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance," IEEE Transaction on Electron Devices, vol. 38, No. 8, pp. 1757-1764.
5-347408
Kao David Y.
Wu Jeff Zhiqiang
Booth Richard
Micro)n Technology, Inc.
LandOfFree
Transistor device structures, and methods for forming such struc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor device structures, and methods for forming such struc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor device structures, and methods for forming such struc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-258381