Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-29
2002-04-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S320000, C438S366000, C438S696000
Reexamination Certificate
active
06365451
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices and integrated circuits, and more particularly to fabrication methods of MOS and bipolar transistors in integrated circuits.
In the fabrication of semiconductor devices, it is well known that parasitic capacitances tend to decrease the operating speed of the devices. Accordingly, the industry is constantly attempting to decrease parasitic capacitance to obtain the concomitant increase in device operating speed.
Such parasitic capacitances arise whenever there are two charge carrying locations in the device or between the device and an external location separated by a dielectric. With the continued miniaturization of semiconductor devices, the distances between these charge carrying locations decreases and the thicknesses of the dielectrics also decreases, thereby increasing the parasitic capacitance within the device being fabricated. Also, the doping levels have been increasing, this also leading to an increase in capacitance.
SUMMARY OF THE INVENTION
The present invention provides small contacts by use of sidewall removals to form the contact openings.
This has the advantage of permitting small source/drains in MOS and small extrinsic bases in bipolar transistors with consequent small junction capacitance.
REFERENCES:
patent: 4873557 (1989-10-01), Kita
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5397722 (1995-03-01), Bashir et al.
patent: 5439839 (1995-08-01), Jang
patent: 5451532 (1995-09-01), Bashir et al.
patent: 5506161 (1996-04-01), Orlowski et al.
patent: 5672530 (1997-09-01), Hsu
patent: 5940711 (1999-08-01), Zambrano
patent: 6017823 (2000-01-01), Shishiguchi et al.
patent: 6177325 (2001-01-01), Jang
“Sub-50NM Gate Length N-MOSFETs With 10 NM Phosphorus Source and Drain Junctions,” 1993 IEEE, pp. 6.2.1-6.2.4 (Mizuki Ono, Masanobu Saito, Takashi Yoshitomi, Claudio Fiegna, Tatsuya Ohguro and Hiroshi Iwai) Electronic Device, Meeting, 1993.
Brady III Wade James
Denker David
Lattin Christopher
Niebling John F.
Telecky , Jr. Frederick J.
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