Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-06
2008-12-02
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S144000, C711S154000, C711S159000
Reexamination Certificate
active
07461209
ABSTRACT:
A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
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Altman Erik R.
Gschwind Michael Karl
Montoye Robert Kevin
Rivers Jude A.
Sathaye Sumedh Wasudeo
International Business Machines - Corporation
Lane Jack A
Nichols Michael R.
Salys Casimer K.
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