4. Electrical computers and digital processing systems: memory
  5. Storage accessing and control
  6. Hierarchical memories

Quinn W. Merrell

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Mechanism handling race conditions in FRC-enabled processors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Microprocessor design support for computer system and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Microprocessor design support for computer system and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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System and method for exclusively writing tag during write alloc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Transfer of cache lines on-chip between processing cores in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Profile ID: LFUS-PAI-P-86956

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