Transceiver with latency alignment circuitry

Details Transceiver with latency alignment circuitry Transceiver with latency alignment circuitry

2006-06-20

2006-06-20

Chace, Christian P. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000, C710S025000, C710S029000, C710S045000, C710S106000, C713S400000, C713S600000

Reexamination Certificate

active

07065622

ABSTRACT:
A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

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